Programmable ESD Protection Structure With Floating Gate
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Solution Overview
Problem
Existing snapback devices like SCRs and LVTSCRs are not suitable for low voltage protection during the assembly of semiconductor devices as they typically provide high impedance, low leakage structures with high breakdown voltage, which are not effective in passive mode.
Innovation Solution
A programmable LVTSCR or snapback NMOS structure is developed with a control gate and a floating gate that can be capacitively coupled and charged via Fowler-Nordheim tunneling, allowing for adjustable breakdown voltage modes by charging the floating gate to specific potentials, enabling low voltage snapback during assembly and high breakdown voltage post-assembly.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a snapback device is designed with high breakdown voltage for post-assembly protection, then it provides high impedance and low leakage, but it becomes ineffective for low voltage protection during assembly
Solution Approach 1:
The patent applies dynamics by making the breakdown voltage of the snapback device adjustable through programming. The device can dynamically switch between high breakdown voltage mode (for post-assembly protection) and low breakdown voltage mode (for during-assembly protection) by controlling the potential of the floating gate, allowing it to adapt to different operational requirements.
Solution Approach 2:
The patent changes the electrical parameter (breakdown voltage) of the snapback device by controlling the potential of the floating gate. By adjusting the floating gate potential between approximately 0-2V and 5-10V, the breakdown voltage can be programmed to switch between low and high modes, enabling the device to serve different protection functions.
2Reliability
If a snapback device provides low impedance for effective low voltage protection during assembly, then it increases leakage current, but this is unacceptable for passive mode operation
Solution Approach 1:
The patent makes the impedance characteristic dynamic by programming the floating gate potential. During assembly, the device is programmed to low impedance state for effective low voltage protection. After assembly, it is programmed to high impedance state to minimize leakage current, thus adapting to different operational phases.
Solution Approach 2:
The patent changes the impedance parameter of the snapback device through floating gate programming. By adjusting the floating gate potential, the device can switch between low impedance (for during-assembly protection) and high impedance (for post-assembly low leakage operation), resolving the contradiction between protection capability and energy loss.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides effective ESD protection with adjustable breakdown voltage, transitioning from low voltage protection during semiconductor assembly to high impedance and low leakage post-assembly, suitable for both low and high voltage scenarios without requiring additional process steps.
Implementation Method 1
The floating gate is typically electrically insulated from the LVTSCR but positioned to facilitate charging of the floating gate by Fowler-Nordheim tunneling
Implementation Method 2
a floating gate positioned to capacitively couple with the control gate
Data Source
AI summary
In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have different charges on it as desired.