Programmable Fault Violation Filter With Hardware Counters
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Solution Overview
Problem
Existing fault detection and filtering methods in electronic devices are susceptible to processor load, resource consumption, and security vulnerabilities, particularly in software-based solutions, and hardware-based methods are expensive and resource-intensive.
Innovation Solution
A programmable fault event monitor and filter system utilizing digital comparators, counters, and an output controller to generate filtered fault event signals based on programmable thresholds, reducing processor load and enhancing robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If software-based filtering and ISR solutions are used, then system implementation is simpler and cost is lower, but processor load increases and reliability decreases due to susceptibility to hacking and malware
Solution Approach 1:
The patent replaces software-based filtering and interrupt service routines with a dedicated hardware filter circuit. This hardware implementation eliminates software vulnerabilities to hacking and malware while maintaining filtering functionality through pure hardware logic that processes comparator outputs independently of the processor.
Solution Approach 2:
The patent introduces a dedicated hardware filter circuit as an intermediary between the comparator and the processor. This intermediate hardware layer processes threshold violation signals without involving software, thereby protecting the system from software-based attacks while reducing processor load.
2Speed
If ISR operates at high execution rate to service interrupts quickly, then response time improves, but power consumption increases
Solution Approach 1:
The patent extracts the filtering function from the processor and implements it in dedicated hardware. This separation allows the processor to remain idle during normal operation while the hardware filter continuously monitors threshold violations, eliminating the need for high-speed processor execution and reducing power consumption.
Solution Approach 2:
The hardware filter circuit operates autonomously without requiring processor intervention. It self-processes comparator outputs, counts violations, and generates filtered fault event signals independently, thereby eliminating the energy-intensive processor ISR loop while maintaining fast response capability.
3Reliability
If hardware-based fault protection using external hardware circuits is implemented, then reliability improves, but cost and device complexity increase
Solution Approach 1:
The patent merges multiple functions into a single integrated hardware filter circuit: threshold violation filtering, counter-based duration monitoring, and fault event signal generation are combined in one circuit block. This integration reduces overall system complexity compared to separate external hardware circuits while maintaining high reliability.
Solution Approach 2:
The hardware filter circuit is designed as a universal solution that handles multiple fault detection scenarios through programmable thresholds and configurable counter limits. A single circuit implementation provides both filtering and duration-based decision making, reducing the need for multiple specialized hardware components.
4Reliability
If software-based fault detection tracks every threshold violation interrupt, then detection completeness improves, but processor resource consumption increases
Solution Approach 1:
The patent extracts the fault tracking function from the processor and implements it in hardware counters within the filter circuit. This allows complete tracking of threshold violations without consuming processor resources, as the hardware circuit independently monitors and counts violations based on comparator outputs.
Solution Approach 2:
The hardware filter circuit acts as an intermediary that completely handles fault detection and counting operations. It processes every comparator output and maintains accurate counts of threshold violations, thereby ensuring detection completeness while the processor remains free for other tasks.
Data Source
AI summary
A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital comparator generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters.