Programmable Fault Violation Filter Hardware
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Solution Overview
Problem
Existing solutions for filtering and fault handling in electronic devices are susceptible to issues such as high processor load, power consumption, and vulnerability to external interference, particularly in safety-critical applications.
Innovation Solution
A fault event monitor and filter system that includes a digital comparator, counters, and an output controller, which generates a filtered fault event signal based on programmable threshold inputs, reducing processor load and enhancing robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If software-based filtering and ISR solutions are used, then fault detection capability is provided, but processor load increases and power consumption increases
Solution Approach 1:
The patent extracts the fault detection and filtering functionality from the processor and implements it in dedicated hardware circuits. The hardware fault detection circuit includes comparators, counters, and logic gates that independently monitor operational parameters and generate fault signals without requiring processor intervention, thereby reducing processor load and power consumption while maintaining reliable fault detection
Solution Approach 2:
The patent introduces hardware intermediary circuits between the operational parameters and the processor. The hardware fault detection circuit acts as an intermediary that pre-processes fault detection, filtering, and signal generation before any processor involvement, enabling the processor to remain unaware of fault conditions and thus reducing its energy consumption
2Reliability
If software-based filtering and ISR solutions are used, then fault detection capability is provided, but the system becomes vulnerable to external interference
Solution Approach 1:
The patent extracts the critical fault detection functionality from the software environment and places it in dedicated hardware circuits that are external to the processor and immune to software-based attacks. The hardware circuit includes comparators, counters, and logic gates that physically detect fault conditions without being susceptible to hacking, malware, or software-based interference
Solution Approach 2:
The patent replaces the software-based fault detection mechanism with a hardware-based mechanism. Instead of using processor instructions and software routines to detect faults, the system uses hardware circuits that physically monitor operational parameters and generate fault signals through deterministic electrical comparisons, eliminating the vulnerability to software-based attacks
3Reliability
If hardware-based fault protection using external hardware circuits is used, then robustness is improved, but cost increases
Solution Approach 1:
The patent merges the fault detection functionality into the existing processor architecture by integrating the hardware fault detection circuit as an on-chip peripheral. The circuit shares the same physical substrate and power supply as the processor, eliminating the need for separate external hardware components and reducing overall system cost while maintaining robustness
Solution Approach 2:
The patent designs the hardware fault detection circuit to serve multiple functions: monitoring various operational parameters (voltage, current, temperature), filtering false positives through counter-based duration detection, and generating appropriate fault signals. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby reducing overall system cost
4Reliability
If hardware-based fault protection using on-chip resources is used, then robustness is improved, but valuable on-chip resources are consumed
Solution Approach 1:
The patent allocates dedicated, dedicated hardware resources specifically for fault detection functionality, separating them from the general-purpose processor resources. The fault detection circuit has its own dedicated comparators, counters, and logic gates that do not share resources with other processor functions, ensuring that robustness is achieved without consuming valuable on-chip resources needed for computational tasks
Data Source
AI summary
A fault event monitor and filter having a digital comparator receiving a digital input value, wherein the digital comparator generates a plurality of outputs based on programmable threshold input values, a first counter coupled to a first output of the plurality of outputs of the digital comparator, a second counter coupled to a second output of the plurality of outputs of the digital comparator, and an output controller with a first input coupled to an output of the first counter and with a second input coupled to an output of the second counter, wherein the output controller to generate a fault event signal based at least partially on signals received from the first and second counters.