Programmable Feed Forward Equalizer Using Capacitive Unit Cells
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Solution Overview
Problem
Current feed forward equalizer (FFE) implementations in integrated circuits are inefficient in terms of power consumption and die area, particularly when designing receivers that operate using both PAM2 and PAM4 modalities, and they do not provide the same signal-to-noise ratio improvement as decision feedback equalizers while being prone to burst error propagation.
Innovation Solution
A programmable feed forward equalizer is implemented using a plurality of unit cells with capacitive elements and clock logic to control switches, allowing for adjustable capacitance and filter coefficients, which are applied as a selected voltage signal to improve signal processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a trans-conductance (gm) stage is used to implement FFE, then the equalization function is achieved, but power consumption and die area increase
Solution Approach 1:
The patent replaces the traditional trans-conductance (gm) stage with a voltage-mode implementation using capacitive elements and switches. This substitution eliminates the need for high-power gm stages while achieving the same equalization function through voltage sampling and weighting, directly reducing power consumption.
Solution Approach 2:
The patent changes the implementation parameter from current-mode (gm stage) to voltage-mode (capacitive sampling). By using capacitors to store voltage samples and switches to control their contribution to the summing node, the system achieves equivalent equalization with significantly lower power dissipation.
2Reliability
If a trans-conductance (gm) stage is used to implement FFE, then the equalization function is achieved, but die area increases
Solution Approach 1:
The patent replaces the large-area trans-conductance (gm) stage with compact voltage-mode circuitry consisting of small capacitive elements and switches. This substitution dramatically reduces the occupied die area while maintaining the equalization function.
Solution Approach 2:
The patent uses multiple identical unit cells, each containing capacitive elements and switches, that can be replicated and pipelined. This modular approach allows efficient use of die area through standardization and reuse of the same circuit blocks across multiple stages.
3Reliability
If decision feedback equalization is used, then signal-to-noise ratio is improved, but burst error propagation occurs
Solution Approach 1:
The patent segments the equalization function into multiple independent unit cells with capacitive elements, each processing signal samples independently. This segmentation avoids the feedback mechanism that causes error propagation while maintaining SNR improvement through parallel processing of signal components.
Solution Approach 2:
The patent extracts and removes the feedback path from the equalization system, replacing it with a feedforward architecture using capacitive sampling. This extraction eliminates the mechanism that causes burst error propagation while preserving the beneficial SNR improvement through selective signal weighting.
4Productivity
If pipelined architecture is implemented, then data rate is increased, but circuit complexity increases
Solution Approach 1:
The patent segments the equalization function into multiple identical unit cells that can be pipelined. Each unit cell is a simple, standardized block containing capacitive elements and switches, making the overall complex high-data-rate system composed of many simple, manageable modules.
Solution Approach 2:
The patent introduces dynamic clock logic to control the timing of switches and capacitive elements in each pipeline stage. This dynamic control enables high data rates by coordinating the operation of multiple pipeline stages, with each stage processing data at the appropriate clock phase.
Data Source
AI summary
A programmable feed forward equalizer (FFE) includes a plurality of unit cells, each unit cell comprising a capacitive element coupled to an input connection by a first switch and coupled to an output connection by a second switch. The FFE also comprises clock logic configured to control the first switch and the second switch so that a selected voltage signal is applied to the capacitive element at a selected time such that the selected voltage signal defines a capacitance of the capacitive element, the clock logic causing the second switch to couple the capacitive element to the output connection so as to apply the selected voltage signal as a filter coefficient to a summing element.