Multiplier-Based Programmable Filters With Pre-Scaling for Lower Power
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Solution Overview
Problem
Existing programmable filters in transceivers face challenges in reducing power consumption and silicon area usage while maintaining high sampling rates, particularly in wide bandwidth implementations.
Innovation Solution
A multiplier-based programmable filter is introduced, utilizing a Booth Radix-8 architecture with pre-scaling circuitry and multiplier circuits that generate pre-scaled multipliers, reduce the number of addition operations, and output carry-sum outputs to increase speed and reduce circuit size, thereby minimizing power consumption and area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional programmable filter architecture is used, then filtering functionality is achieved, but power consumption and silicon area are excessive
Solution Approach 1:
The pre-scaling circuitry pre-calculates scaled versions of the multiplier (e.g., 2x, 4x, 8x) before the multiplication operation. This preliminary action reduces the computational burden during the actual filtering operation, thereby reducing power consumption while maintaining filtering functionality
Solution Approach 2:
The filter architecture is segmented into distinct functional blocks: pre-scaling circuitry, multiplier circuits, and adder circuits. This segmentation allows each block to be optimized independently, reducing overall silicon area while maintaining the required filtering performance
2Speed
If traditional multiplication operations are used, then filtering accuracy is maintained, but operational speed is reduced
Solution Approach 1:
The pre-scaling circuitry prepares scaled multipliers in advance, so that during the actual filtering operation, fewer addition operations are required. This preliminary preparation increases operational speed while the carry-sum output format ensures filtering accuracy is maintained
Solution Approach 2:
The multiplier output format is changed from traditional sum-output to carry-sum output. This parameter change in the output format allows for faster operation by separating the carry and sum components, while maintaining the precision required for accurate filtering
3Area of stationary object
If full multiplication operations are performed, then filtering precision is achieved, but circuit area is excessive
Solution Approach 1:
The pre-scaling circuitry pre-computes scaled versions of the multiplier, which reduces the number of addition operations needed in the subsequent stages. This preliminary computation reduces the required circuit area while maintaining filtering precision through the carry-sum output format
Solution Approach 2:
The carry component is extracted separately from the sum component in the carry-sum output format. This extraction allows for more efficient circuit implementation with reduced area, while the precision is maintained through the separate handling of carry and sum values
4Use of energy by moving object
If multiple addition operations are used, then filtering accuracy is maintained, but power consumption increases
Solution Approach 1:
The pre-scaling circuitry performs scaling operations in advance, reducing the number of addition operations required during the main filtering operation. This reduces power consumption while the carry-sum format preserves filtering accuracy
Solution Approach 2:
The output format is changed to carry-sum representation, which requires fewer addition operations compared to traditional formats. This parameter change reduces power consumption while maintaining the precision needed for accurate filtering through separate carry and sum paths
Data Source
AI summary
In some embodiments, a multiplier-based programmable filter comprises a pre-scaling circuit, a first multiplier circuit coupled to a first output of the pre-scaling circuit and a second output of the pre-scaling circuit, and a second multiplier circuit coupled to the first output of the pre-scaling circuit and the second output of the pre-scaling circuit. In some embodiments, the multiplier-based programmable filter also comprises a first adder coupled to a first output of the first multiplier circuit and a second output of the first multiplier circuit, a second adder coupled to a first output of the second multiplier circuit and a second output of the second multiplier circuit, first register coupled to an output of the first adder and an input of the second adder, and a second register coupled to an output of the second adder.