Programmable Fine Delay Circuit for Uniform Delay Tuning
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Solution Overview
Problem
Existing fine delay circuits exhibit high local variability and poor linearity and uniformity, particularly in analog designs, and limited sensitivity to environmental factors like power, voltage, and temperature, which complicates their integration with coarse delay circuits.
Innovation Solution
A fine delay circuit design incorporating a variable resistive element and capacitive elements controlled by switches, allowing for programmable delay ranges and improved capacitance tuning, which reduces variability and enhances sensitivity to environmental factors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If analog delay circuits are used to achieve good resolution and sensitivity to power, voltage, and temperature, then sensitivity to environmental factors is improved, but linearity and uniformity deteriorate
Solution Approach 1:
The delay circuit is divided into multiple identical delay units, each contributing a fixed delay amount. By cascading these segmented units, the total delay is achieved through repetition rather than continuous analog adjustment, improving linearity and uniformity while maintaining sensitivity to environmental factors through proper sizing of individual units.
Solution Approach 2:
The invention changes the delay parameter in discrete steps by switching between different delay unit configurations rather than continuous analog adjustment. This allows the circuit to maintain sensitivity to environmental factors while achieving better linearity through controlled discrete transitions.
2Manufacturing precision
If digital delay circuits are used to achieve good linearity and uniformity, then manufacturing precision is improved, but sensitivity to power, voltage, and temperature deteriorates
Solution Approach 1:
Each delay unit is designed with specific local characteristics (capacitance and resistance values) that provide both the discrete digital-like switching behavior for linearity and the analog-like sensitivity to environmental factors. The local quality of each unit combines both desirable properties.
3Adaptability or versatility
If coarse delay circuits are integrated with fine delay circuits, then delay range is improved, but delay mismatch and variability increase
Solution Approach 1:
The total delay range is segmented into coarse and fine portions, where the fine delay units are designed to compensate for mismatches in the coarse delay portion. This segmentation allows each portion to be optimized independently while maintaining overall precision.
Solution Approach 2:
The fine delay circuit acts as a feedback mechanism to correct delay mismatches introduced by the coarse delay circuit. By adjusting the fine delay portion, the system compensates for variations in the coarse portion, reducing overall delay mismatch.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves low delay mismatch and improved uniformity with programmable delay ranges, enhancing integration with coarse delay circuits and sensitivity to power, voltage, and temperature variations.
Implementation Method 1
a first capacitive element connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element connected in series with the second switch and the third node
Implementation Method 2
controlling a variable resistive device arranged in parallel with the first capacitive device and a second capacitive device to control a delay of a signal input to the fine delay circuit
Implementation Method 3
a first inverter connected to the first node and a second node, and a second inverter connected to the third node and a fourth node
Data Source
AI summary
A circuit includes a first node, a first inverter connected to the first node and a second node. A variable resistive element is connected to the second node and a third node. A first switch is connected to the second node, a first capacitive element is connected in series with the first switch and the third node, a second switch connected to the second node, a second capacitive element is connected in series with the second switch and the third node, and a second inverter is connected to the third node and a fourth node.