Programmable Forwarding Pipeline Using Packet Header Summaries
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Solution Overview
Problem
Current packet processing systems in data centers face inefficiencies due to the use of fixed function hardware for parsing and forwarding, which can lead to dropped packets if the parser is not fast enough to process incoming data streams, and require complex configurations for handling different packet types.
Innovation Solution
A hardware-based data processing unit (DPU) employs a programmable parser template register to store summary information about parsed packet headers, enabling efficient processing and forwarding by using this information in a programmable forwarding pipeline, allowing for flexible allocation of storage and lookups across multiple logical tables.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fixed function hardware is used for packet parsing and forwarding, then device complexity is reduced and ease of manufacture is improved, but adaptability to different packet types deteriorates and productivity decreases due to packet drops
Solution Approach 1:
The patent implements a dynamic forwarding pipeline where functional blocks can be selectively activated and deactivated based on packet type. The system transitions from static fixed-function hardware to a dynamic reconfigurable architecture that adapts its processing path in real-time, allowing the same hardware to efficiently handle multiple packet formats without physical reconfiguration
Solution Approach 2:
The patent creates a universal forwarding pipeline that can process multiple packet types (Ethernet, VLAN, IP versions 4 and 6, TCP, UDP) using the same hardware infrastructure. The parser and forwarding pipeline are designed to be type-agnostic, with conditional logic that routes different packet formats through appropriate processing stages, eliminating the need for separate dedicated hardware for each packet type
2Device complexity
If fixed function hardware is used for packet parsing, then device complexity is reduced, but adaptability to different packet types and processing requirements deteriorates
Solution Approach 1:
The system employs dynamic configuration where the forwarding pipeline's functional blocks are activated or deactivated based on the parsed packet type. This allows a single unified hardware design to adapt its behavior in real-time without requiring complex physical reconfiguration, maintaining relatively simple device architecture while achieving high adaptability
Solution Approach 2:
The patent changes operational parameters (which functional blocks are active, which parsing rules are applied) based on packet type identification rather than changing the physical hardware configuration. This allows the same device structure to exhibit different functional behaviors by modifying control parameters and activation states of various processing blocks
3Device complexity
If the parser processes incoming data streams slowly, then device complexity is reduced, but reliability deteriorates due to packet drops
Solution Approach 1:
The patent segments the packet processing function into distinct modular blocks: a parser that extracts header information, a forwarding pipeline with multiple functional blocks for different processing operations, and lookup tables for decision-making. This segmentation allows each component to be optimized independently and enables parallel processing paths that increase overall throughput and reliability without requiring overly complex monolithic designs
Solution Approach 2:
The system performs preliminary parsing of packet headers to identify packet type and extract key fields before routing to specific processing paths. This preliminary action allows the forwarding pipeline to be pre-configured with the appropriate functional blocks for that packet type, enabling faster processing and reducing the likelihood of packet drops due to insufficient processing speed
Data Source
AI summary
This disclosure describes techniques that include storing, during parsing of a data unit or a network packet, information (i.e., “summary information”) that identifies how the network packet has been process and/or other aspects of the parsing process. In one example, this disclosure describes a method that includes parsing a packet header from a data unit, wherein parsing the packet header includes storing in result vector storage each of a plurality of data items derived from the packet header, the result vector storage having a result vector format defining fields within the result vector storage for storing each of the plurality of data items; storing in template storage, for each of the plurality of data items, summary information about the plurality of data items stored in the result vector storage; and processing, by the packet-processing integrated circuit and based on the summary information and the plurality of data items, the network packet.