Programmable Frequency Multiplier for Low-Noise Integer Scaling
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Solution Overview
Problem
Existing frequency multiplication devices struggle with achieving low phase noise and wide frequency range operation, particularly in providing programmable frequency multiplication by arbitrary integer factors, which is essential for modern communication systems, and they often suffer from SNR degradation due to double sideband conversion and increased complexity.
Innovation Solution
A programmable frequency multiplier using an array of Complex Frequency Shifters (CFS) and programmable switches, which allows for direct interconnection of cascaded stages without additional circuitry, enabling frequency multiplication by arbitrary integer factors with low phase noise and minimal delay, and providing in-phase and quadrature components for use in other system components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If mixer-based frequency multiplication is used, then frequency multiplication capability is achieved, but phase noise increases and SNR degrades
Solution Approach 1:
The frequency multiplication process is segmented into multiple stages, each performing a partial multiplication function. The overall multiplication factor N is decomposed into smaller factors that are applied sequentially through multiple mixer stages, allowing each stage to operate with lower gain and reduced phase noise accumulation.
Solution Approach 2:
Multiple frequency multiplication stages are nested in a cascaded configuration where the output of one stage feeds into the next. Each stage is embedded within the overall system hierarchy, with intermediate frequency conversions and selective filtering nested between multiplication stages to maintain signal integrity and minimize noise.
2Productivity
If cascade of frequency doublers is used to achieve high multiplication ratios, then frequency multiplication capability is improved, but device complexity increases
Solution Approach 1:
The mixer circuits are designed to perform multiple functions: frequency multiplication, frequency conversion, and signal mixing. The same hardware infrastructure supports different multiplication ratios by reconfiguring the input signal paths and local oscillator frequencies, eliminating the need for dedicated circuits for each multiplication factor.
Solution Approach 2:
The system employs dynamic reconfiguration capabilities where the multiplication factor can be changed by adjusting the local oscillator frequencies and signal routing in real-time. This dynamic adaptability allows a single fixed-frequency device to perform multiple multiplication functions, reducing overall system complexity.
3Productivity
If quadrature splitting circuit is repeated in every stage, then frequency multiplication is achieved, but bandwidth is reduced
Solution Approach 1:
Multiple quadrature splitting functions are merged into a single shared quadrature splitting circuit located at the input stage. The split quadrature signals are then distributed to all subsequent multiplication stages through common signal paths, eliminating the need for repeated quadrature splitters and preserving bandwidth.
Solution Approach 2:
Intermediate frequency conversion stages serve as mediators between the single quadrature split and multiple multiplication operations. The intermediate frequencies are generated once and then used across multiple stages, acting as a shared resource that reduces the total number of quadrature splitting operations required.
4Measurement precision
If direct analog multiplication is used, then phase noise is reduced, but adaptability to different frequency ranges is limited
Solution Approach 1:
The system achieves adaptability by dynamically changing operating parameters such as local oscillator frequencies, signal routing configurations, and mixer bias conditions. These parameter adjustments allow the same analog multiplication hardware to operate effectively across different frequency ranges and for different multiplication factors without sacrificing phase noise performance.
Data Source
AI summary
A programmable frequency multiplier device which includes a frequency doubler section configured to receive an input signal having a frequency f, and to output doubled signals, each of the doubled signals having a frequency 2n×f (n=0, 1, 2, . . . ); a selector section configured to select a plurality of the doubled signals output from the frequency doubler section, and to output the plurality of the selected doubled signals as selected signals; and a frequency summation section configured to multiply the selected signals, and to output a multiplied signal having a frequency fout=f×(m020+m121+ . . . +mk2k+ . . . +mn2n), wherein mk=0 or 1, and k=0, 1, . . . , n.