Programmable Hashing Cache Controller for Image Scan Line Conflict Resolution
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Solution Overview
Problem
Current cache designs face high cache miss rates when handling large images, as only a small number of scan lines can be kept in the cache due to direct mapping schemes, leading to data preloading issues and increased latency.
Innovation Solution
A programmable hashing address method is employed to generate unique cache indices for each scan line, preventing multiple scan lines from hitting the same bank and set, thereby improving cache hit rates through adaptive bit shift operations based on image size and cache capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a direct mapping scheme is used for cache addressing, then the hardware complexity and latency are reduced, but the cache hit rate deteriorates because multiple scan lines map to the same bank and set
Solution Approach 1:
The patent applies parameter changes by introducing a programmable hash function that transforms the address mapping parameters. Instead of direct mapping, the system uses a configurable hash function with adjustable parameters (such as polynomial coefficients or bit shift amounts) to redistribute scan lines across different cache banks and sets, thereby reducing conflicts while maintaining manageable hardware complexity
Solution Approach 2:
The patent implements dynamics by making the hash function programmable and configurable rather than fixed. The hash parameters can be dynamically adjusted based on image characteristics, cache size, and access patterns, allowing the system to adapt to different scenarios and optimize cache hit rates without requiring complete hardware redesign
2Reliability
If the cache size is increased to hold more scan lines, then the cache hit rate improves, but the data processing latency increases due to longer access times
Solution Approach 1:
The patent applies segmentation by dividing the image data into smaller units (scan lines or blocks) and distributing them across multiple cache banks and sets through the hash function. This segmentation allows the system to maintain a larger effective cache capacity without increasing the physical cache size, as multiple small segments can be managed concurrently across parallel cache structures, reducing access latency
3Reliability
If a fully associative cache is used, then the cache hit rate improves by allowing any memory location to map to any cache location, but the hardware complexity and latency increase
Solution Approach 1:
The patent introduces an intermediary hash function layer between the memory address and the cache selection logic. This intermediary component processes the address through a configurable hash function to determine cache bank and set, acting as a mediator that simplifies the selection process compared to full associativity while still achieving high hit rates through intelligent address transformation
Data Source
AI summary
A method for controlling access of a cache includes at least following steps: receiving a memory address; utilizing a hashing address logic to perform a programmable hash function upon at least a portion of the memory address to generate a hashing address; and determining an index of the cache based at least partly on the hashing address.