Programmable Header Switch Cells for Local Power and Hold Timing Control
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Solution Overview
Problem
Conventional power management integrated circuits (PMICs) face challenges in reducing power consumption and mitigating hold failures within power blocks, as they often require global voltage settings that do not allow for independent control of power blocks, leading to inefficient power usage and performance impacts.
Innovation Solution
The implementation of individually programmable head switch cells within power blocks, which can be dynamically turned on or off, allowing for localized power control and optimized power consumption, and mitigating hold failures by selectively programming head switch cells to reduce power consumption and increase timing delay in critical regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If global voltage settings are used for power blocks, then power management is simplified, but power consumption efficiency deteriorates and hold failures cannot be mitigated
Solution Approach 1:
The patent segments the power control system by introducing individually programmable head switch cells for each power block, allowing independent control of power consumption for each block rather than using a single global voltage setting for all blocks
Solution Approach 2:
The patent applies local quality by enabling different voltage settings and power states for different power blocks based on their specific requirements, allowing critical regions to be differentiated from non-critical regions for optimized power management
2Ease of operation
If global voltage settings are used for power blocks, then control is simplified, but hold failures worsen due to inability to provide timing delay in critical regions
Solution Approach 1:
The patent divides the power control into segmentable units (head switch cells) that can be individually programmed to provide timing delay where needed, allowing critical regions to be identified and protected from hold failures independently
Solution Approach 2:
The patent implements preliminary action by pre-programming head switch cells with specific timing characteristics before operation, allowing timing delay to be built into critical regions in advance to prevent hold failures
3Use of energy by moving object
If head switch cells are individually programmable, then power consumption is reduced and hold failures are mitigated, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a standardized head switch cell architecture that can be replicated across multiple power blocks, where each cell provides the same set of functions (power switching, timing delay, programmability) reducing overall system complexity despite individual customization
Data Source
AI summary
Certain aspects of the present disclosure generally relate to optimizing, or at least reducing, power consumption and/or hold timing issues within an integrated circuit (IC). One example IC generally includes a global power supply rail and a first power block. The first power block includes a first plurality of head switch cells coupled to the global power supply rail. Each head switch cell includes a head switch coupled between the global power supply rail and a power node for the head switch cell. The first plurality of head switch cells is configured such that a first set of the first plurality of head switch cells can be programmed on and a second set of the first plurality of head switch cells can be programmed off.