Programmable IC Routing Network for Asynchronous Data Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As integrated circuits evolve with increasing voltage and frequency domains, conventional circuits face challenges in transferring signals quickly due to limitations in metal conductors and require complex timing control, leading to issues like increased capacitance, delay, and significant clock loading, especially in devices with programmable resources that need synchronous communication.
Innovation Solution
A programmable integrated circuit with a matrix of configurable blocks and a routing network featuring programmable interconnect points with buffers enables asynchronous communication, using transmission lines to convert single-ended data to dual rail data and back, facilitating wave pipelining and reducing clock loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous communication with clock signals is used, then timing control is enabled, but area overhead and device complexity increase
Solution Approach 1:
The patent extracts the clock signal distribution network from the communication infrastructure, replacing it with asynchronous handshaking protocols. This removes the need for extensive clock routing circuits and reduces area overhead while maintaining timing control through event-driven synchronization.
Solution Approach 2:
The patent introduces handshake signals as intermediaries between communicating circuit blocks. These mediator signals coordinate data transfer without requiring shared clock domains, enabling timing control through request-acknowledge protocols rather than synchronous clock distribution.
2Speed
If metal conductor width is increased to increase signal transfer speed, then speed improves, but capacitance and delay increase
Solution Approach 1:
The patent employs wave pipelining that periodically activates buffer circuits along the signal path. Instead of continuously driving strong signals through wide conductors, the system uses periodic wavefronts that propagate through the circuit, reducing the capacitive load on interconnects while maintaining high effective data rate.
Solution Approach 2:
The patent replaces the physical mechanism of wide metal conductors (mechanical/electrical system) with a temporal mechanism using pipelined data transmission. Data is broken into waves that progress through the circuit over time, substituting spatial bandwidth with temporal multiplexing to reduce capacitance.
3Productivity
If flip flops are inserted in interconnects to pipeline data, then throughput increases, but clock loading increases
Solution Approach 1:
The patent introduces dynamic pipelining where the number and position of pipeline stages are not fixed but adapt based on data flow requirements. Buffer circuits can be dynamically enabled or disabled, allowing the pipeline depth to adjust to workload conditions, thereby improving throughput while minimizing unnecessary clock loading.
Solution Approach 2:
The patent implements self-service pipelining where the data flow itself triggers the activation of pipeline stages. Instead of requiring a global clock to drive all flip-flops, the pipeline stages automatically activate when data arrives, using the data signal itself to control the timing, thus reducing clock loading while maintaining throughput.
4Adaptability or versatility
If more interconnects are provided for programmability, then adaptability improves, but area overhead increases
Solution Approach 1:
The patent designs interconnect resources with multi-functionality, where the same physical interconnect structure can be configured to serve different routing purposes through reconfigurable switch matrices. This universal interconnect fabric provides high adaptability for programmable logic while minimizing area overhead by avoiding dedicated interconnect paths for each possible connection.
Data Source
AI summary
A programmable integrated circuit is disclosed. The programmable integrated circuit comprises a matrix of circuit blocks, each circuit block of the matrix of circuit blocks comprising configurable blocks; and a routing network coupled to the matrix of circuit blocks, the routing network having a plurality of programmable interconnect points comprising buffers enabling asynchronous communication. A method of asynchronously routing data in an integrated circuit is also disclosed.