Programmable IC Sub-Circuit Sleep Control Using GWE Masking

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Solution Overview

Problem

Current methods for reducing dynamic power consumption in programmable integrated circuits are either time-consuming, complex, or do not provide the desired results, particularly in scenarios where quick power management is required.

Innovation Solution

The method involves using global write enable (GWE) signal masking and separate configuration memory cells to control the responsiveness of sub-circuits, allowing for dynamic power reduction by putting selected modules to sleep without altering the underlying design or requiring partial reconfiguration, while preserving logic states and enabling modules to wake up quickly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of energy

If partial reconfiguration is used to deactivate a module, then dynamic power consumption is reduced, but storage for blank bitstream is required and reconfiguration time increases

Engineering Contradiction:
Improvedynamic power consumptionVSAvoidreconfiguration time
Core Design Contradiction:
Loss of energyVSLoss of time

Solution Approach 1:

The patent pre-configures mask bits in configuration memory cells during the initial programming phase, so that when power reduction is needed, only a simple global control signal change is required rather than performing time-consuming reconfiguration. This preliminary setup enables rapid activation/deactivation of circuitry without repeated reconfiguration operations.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent divides the configuration control into individual mask bits for different regions or circuit elements, allowing selective deactivation of specific sub-circuits while keeping others active. This segmentation enables fine-grained power management without requiring complete reconfiguration of the entire device.

Inventive Principle:
Principle #1Segmentation

2Loss of energy

If partial reconfiguration is used to deactivate a module, then dynamic power consumption is reduced, but device complexity increases due to blank module requirements

Engineering Contradiction:
Improvedynamic power consumptionVSAvoidconfiguration management complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent uses existing configuration memory cells and global control signals for dual purposes: normal operation control and power management. The mask bits in configuration memory cells serve both to define circuit functionality and to enable/disable circuitry for power savings, eliminating the need for separate blank module structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent enables circuitry to self-manage its power state through the interaction of global control signals with locally-configured mask bits. Each sub-circuit's activation state is determined by the combination of the global signal and its own mask bit configuration, allowing distributed autonomous power management without complex centralized control.

Inventive Principle:
Principle #25Self-service

3Loss of energy

If clock gating logic is added to reduce dynamic power consumption, then power is saved, but design complexity increases

Engineering Contradiction:
Improvedynamic power consumptionVSAvoiddesign complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent merges the power management function with the existing global control signal infrastructure. Instead of adding separate clock gating logic, the patent combines power control capabilities into the global write enable and other control signals that already distribute timing and control information across the device, eliminating the need for additional dedicated gating circuits.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent makes global control signals multi-functional by having them serve both their original control purposes and new power management functions. The same global write enable signal that controls normal operation also controls activation/deactivation for power savings when combined with mask bit configuration, eliminating the need for separate power control logic.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Loss of energy

If global control signals are used to deactivate sub-circuits, then power consumption is reduced and design is simplified, but not all sub-circuits can be selectively controlled

Engineering Contradiction:
Improvepower consumptionVSAvoidselective control capability
Core Design Contradiction:
Loss of energyVSAdaptability or versatility

Solution Approach 1:

The patent segments the global control mechanism by introducing region-specific or circuit-element-specific mask bits in configuration memory cells. This allows the same global control signal to have different effects on different sub-circuits based on their individual mask bit configurations, enabling selective control without requiring separate control signals for each element.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by configuring mask bits specifically for each region or circuit element to match its power management requirements. Different sub-circuits can have different mask bit settings, allowing tailored power control strategies for different parts of the device while using a unified global control signal approach.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS8633730B1Power control using global control signal to selected circuitry in a programmable integrated circuit
Publication Date: 2014.01.21 XILINX INC
  • US8633730B1 patent drawing
  • US8633730B1 patent drawing
  • US8633730B1 patent drawing

AI summary

When a first sub-circuit of a programmable integrated circuit (“IC”) is to be deactivated, a global write enable (GWE) signal is deasserted. In response to deassertion of the GWE signal and a first memory cell associated with the first sub-circuit being in a first state, flip-flops in the first sub-circuit are disabled from changing state. In response to memory cells associated with sub-circuits other than the first sub-circuit being in a second state, flip-flops in the other sub-circuits are enabled to change state. When the first sub-circuit is to be activated, the GWE signal is asserted. Logic implemented by the first sub-circuit is preserved between the deasserting and the asserting of the GWE signal. In response to assertion of the GWE signal and the first memory cell associated with the first sub-circuit being in the first state, flip-flops in the first sub-circuit are enabled to change state.