Programmable IC Configuration Memory for SEU-Critical Logic
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Solution Overview
Problem
Traditional programmable integrated circuits (ICs) are susceptible to single event upsets (SEUs) due to cosmic and alpha particle collisions, leading to increased failure rates and reduced mean time to failure, especially as chip geometries shrink and supply voltages decrease.
Innovation Solution
Implementing a programmable IC with a mix of 6T and 12T SRAM configuration memory cells, where critical portions of the circuit design are programmed using 12T cells for enhanced immunity to SEUs, and non-critical portions use 6T cells, allowing for flexible resource allocation and reduced footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If 6T configuration memory cells are used in traditional programmable ICs, then the IC footprint is compact and resource utilization is efficient, but the susceptibility to single event upsets (SEUs) increases leading to higher failure rates
Solution Approach 1:
The patent applies local quality by differentiating between critical and non-critical portions of the circuit design. Only critical portions are implemented using 12T configuration memory cells with enhanced SEU immunity, while non-critical portions use standard 6T cells. This selective application of radiation-hardened cells reduces the overall impact on IC footprint while providing targeted reliability improvement where it is most needed.
2Reliability
If 12T configuration memory cells are used for all circuit portions, then SEU immunity is maximized, but the IC footprint increases and resource efficiency decreases
Solution Approach 1:
The patent segments the circuit design into critical and non-critical portions, and accordingly segments the configuration memory into 12T and 6T cells. This segmentation allows the system to allocate radiation-hardened 12T cells only to critical functions that require enhanced SEU immunity, while using standard 6T cells for non-critical functions. The result is optimized resource allocation that balances reliability requirements with device complexity and resource efficiency.
3Productivity
If chip geometries are reduced and supply voltages are lowered to improve integration density, then manufacturing capability and power efficiency improve, but the likelihood of SEUs increases
Solution Approach 1:
The patent addresses the reliability issue arising from reduced chip geometries and supply voltages by changing the physical parameter of the configuration memory cells. Specifically, it uses 12T cells for critical portions instead of 6T cells. The 12T cell architecture provides a larger storage node capacitance and higher noise margin, making it more resistant to charge collection from cosmic and alpha particles. This parameter change enables the system to maintain reliability despite the trends toward smaller geometries and lower voltages that improve integration density.
Data Source
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AI summary
To implement a circuit design on a programmable integrated circuit (IC) (100), first data are generated (202) for implementing the circuit design. Critical and non-critical portions of the circuit design with respect to Single Event Upsets (SEus) are determined (206), and second data are generated (210, 212) for programming configuration memory cells of the programmable IC to implement the circuit design. A first subset of the second data is assigned to program a first type of configuration memory cells (118) to implement the critical portion of the circuit design on a first subset of programmable logic resources (102) and a first subset of programmable interconnect resources (106) of the programmable IC. A second subset of the second data is assigned to program a second type of configuration memory cells (120) to implement the non-critical portion of the circuit design on a second subset of programmable logic resources (104) and a second subset of programmable interconnect resources (108). The second data are stored (214) in an electronically readable storage medium. The memory cells of the first type of configuration memory cells are less susceptible to SEUs than the memory cells of the second type of configuration memory cells.