Programmable Impedance Chain for Adjustable Analog Weights
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Solution Overview
Problem
Existing analog integrated circuits face challenges in implementing neural networks due to the need for adjustable weights, which are difficult to achieve with fixed resistors, leading to high power consumption and impracticality in large systems, and current solutions for variable impedance are not feasible for practical use.
Innovation Solution
A programmable impedance circuit using a chain of nominally identical two-port elements with switches, allowing for dynamic configuration of impedance values post-manufacture, enabling adjustable impedance without the limitations of prior art solutions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If fixed resistors are used for weights in analog neural networks, then manufacturing simplicity is improved, but adaptability for training and inference is worsened
Solution Approach 1:
The patent applies the dynamics principle by making the previously fixed resistor values changeable through a digital control mechanism. Each resistor is paired with a digital-to-analog converter (DAC) that can dynamically adjust the resistance value based on digital weight values stored in memory, enabling the system to transition from static to adaptive weight configuration for both training and inference phases.
Solution Approach 2:
The patent introduces digital-to-analog converters (DACs) as intermediary components between the digital control domain and the analog computation domain. These DACs serve as mediators that translate digital weight values into corresponding analog resistance values, allowing digital control of analog circuit parameters without directly modifying the physical resistor structure.
2Adaptability or versatility
If variable resistors are used to enable adaptable weights, then adaptability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by updating resistor values only when weight changes are required (during training or reconfiguration), rather than continuously. The digital control mechanism allows the system to maintain stable analog weights during inference operations while enabling periodic updates to weight values based on stored digital representations, reducing unnecessary power consumption from continuous adjustment.
Solution Approach 2:
The patent uses copying by maintaining digital copies of weight values in memory that can be stored without power (non-volatile). These digital copies serve as templates that can be quickly loaded and converted to analog values when needed, eliminating the need for continuous analog adjustment mechanisms and reducing power consumption during weight storage and retrieval operations.
3Adaptability or versatility
If R-2R ladder networks are used for multiply operation, then adaptability is improved, but probe current requirements increase overall power consumption
Solution Approach 1:
The patent applies segmentation by dividing the weight adjustment function into separate digital and analog domains. The digital domain handles weight value storage and selection, while the analog domain performs the actual multiplication operation. This segmentation allows the system to use simple, low-power analog resistors for the multiply operation while maintaining adaptability through digital control, avoiding the need for high-current probe mechanisms in the analog path.
4Device complexity
If time-division multiplexing is used for large networks, then device complexity is reduced, but weight reconfiguration time increases
Solution Approach 1:
The patent implements preliminary action by pre-storing all weight values in digital form in memory before they are needed for computation. This allows the system to quickly load and convert weight values during operation without requiring time-consuming sequential adjustment mechanisms. The digital weights are prepared in advance and can be rapidly converted to analog values when needed, reducing reconfiguration time while maintaining the ability to handle large networks.
Data Source
AI summary
A programmable impedance element consists of a plurality of nominally identical two-port elements, each two-port element having an impedance element and two switches, the two-port elements arranged in a chain fashion with a structured set of switches such that a range of impedances can be obtained from each cell by dynamically changing the connections between the impedance elements in the cell. The common cell is constructed by connecting the nominally identical two-port impedance elements in a way that the number of possible combinations of the impedance elements is reduced to the subset of all possible combinations that uses the minimum possible number of connections. This structure allows the creation of matched impedances using industry standard devices. The connections between impedance elements are switches that may be “field-programmable,” i.e., that may be set on the chip after manufacture and configured during operation of the circuit, or alternatively may be mask programmable.