Programmable Impedance Memory Device With Lateral Transistor Structures
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Solution Overview
Problem
At advanced technology nodes, CBRAM-type memory elements face challenges in providing sufficient current for erase operations due to smaller transistor channel widths, leading to difficulties in programming and erasing memory elements effectively.
Innovation Solution
The memory device architecture incorporates independent plate structures and gate extensions that surround storage contacts, forming lateral transistor structures to increase current availability and reduce leakage, allowing for effective programming and erasing of CBRAM elements by applying specific voltage potentials to bit lines and plate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor channel widths are reduced to achieve higher density at advanced technology nodes, then storage element density is improved, but current availability for erase operations deteriorates
Solution Approach 1:
The patent introduces plate structures that extend in a direction substantially perpendicular to the bit line, creating a three-dimensional current path through the storage element. This vertical dimension allows current to flow through the entire thickness of the storage element, providing sufficient erase current even when transistor channel widths are reduced for higher density.
Solution Approach 2:
The plate structures serve as intermediary elements between the bit line and the storage element active region. By positioning plate structures at specific locations (such as at ends of the storage element or surrounding storage contacts), they mediate and enhance the current flow through the storage element, ensuring adequate current availability for erase operations without requiring larger transistors.
2Productivity
If transistor size is reduced for higher density, then device integration is improved, but programming and erasing effectiveness deteriorates
Solution Approach 1:
By extending plate structures in the vertical dimension perpendicular to the bit line, the patent creates enhanced current paths that pass through the storage element. This dimensional approach ensures reliable programming and erasing operations even with smaller transistors, as the current flow is augmented by the plate structure geometry rather than relying solely on transistor channel dimensions.
Solution Approach 2:
The patent modifies the electrical parameters of the system by introducing plate structures that change the current distribution and voltage profiles during programming and erasing operations. By applying voltages to plate structures in addition to bit lines, the effective electrical parameters (current magnitude, voltage stress) across the storage element are enhanced, ensuring reliable operation despite reduced transistor size.
3Ease of manufacture
If conventional memory architecture is used, then manufacturing simplicity is maintained, but current flow during programming operations is insufficient
Solution Approach 1:
The patent merges plate structures with existing memory architecture components such as bit lines and storage contacts. By combining these elements into an integrated structure where plate structures are positioned to work in conjunction with conventional components, the design enhances current flow without requiring complete architectural redesign, thus maintaining manufacturing simplicity while improving programming capability.
Solution Approach 2:
Plate structures are introduced as intermediary elements that connect to and enhance the functionality of conventional memory components. These plate structures mediate the current flow between bit lines and storage elements, providing additional current pathways that improve programming effectiveness while being integrated into the existing manufacturing process flow.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances current flow during programming operations, such as erasing CBRAM elements, and ensures electrical isolation of storage elements, improving overall memory device performance at smaller technology nodes.
Implementation Method 1
In some CBRAM elements, switching layers can undergo an oxidation-reduction reaction to arrive at such changes in resistance
Implementation Method 2
The oxidation-reduction reaction may, or may not, include ion conduction
Data Source
AI summary
A memory device can include at least one plate structure formed over a semiconductor substrate; an active region formed within the semiconductor substrate without lateral isolation structures; a plurality of bit line contact groups, each including bit line contacts to the active region disposed in a first direction; a plurality of storage contact groups, each including storage contacts to the active region disposed in the first direction; a plurality of gate structures, each including a main section extending in the first direction, and disposed between one bit line contact group and an adjacent storage contact group; and a two-terminal storage element disposed between each bit line contact and the at least one plate structure.