Programmable Instruction Buffering for Deterministic Pipeline Timing
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Solution Overview
Problem
Data processing systems with pipelined processing face variability in instruction fetch times due to factors like caching and page mapping faults, leading to inconsistent execution times for sequences of instructions.
Innovation Solution
A processing pipeline with fetch circuitry, buffers, and buffer control circuitry that can stall and restart a stallable portion downstream of the buffers, accumulating a burst of instructions based on a programmable trigger, allowing for deterministic timing independent of instruction fetch delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If instructions are fetched from memory in a pipelined processing system, then instruction throughput is improved through parallelism, but execution time becomes inconsistent due to variable fetch delays from caching and page mapping faults
Solution Approach 1:
The system performs preliminary actions by accumulating a predetermined number of instructions in buffers before execution. The buffer control circuitry stores fetched instructions in advance and only releases them to the execution pipeline when a complete set is available, ensuring that execution always starts with a full buffer regardless of variable fetch times. This preliminary accumulation eliminates execution time variability while maintaining high throughput through parallel fetching.
2Productivity
If the processing pipeline continues operating without interruption, then productivity is maintained, but deadlock may occur when downstream stages cannot consume instructions fast enough
Solution Approach 1:
The buffer control circuitry implements feedback control by continuously monitoring the number of accumulated instructions in the buffers. When the buffer reaches a predetermined level, the control circuitry automatically stalls the fetch stage to prevent overflow and potential deadlock. This feedback mechanism ensures the pipeline operates within safe bounds, preventing deadlock while maximizing throughput by keeping the pipeline full when possible.
3Loss of time
If the pipeline is stalled to wait for instructions, then execution consistency is improved, but productivity decreases due to pipeline idle time
Solution Approach 1:
The system performs preliminary accumulation of instructions in buffers before execution begins. By gathering a predetermined number of instructions in advance and only then releasing them to the execution pipeline, the system ensures consistent execution timing without requiring stalls during actual execution. The preliminary buffering action separates the variable-fetch phase from the deterministic-execution phase, maintaining both consistency and throughput.
Data Source
AI summary
A processing system 2 includes a processing pipeline 12, 14, 16, 18, 28 which includes fetch circuitry 12 for fetching instructions to be executed from a memory 6, 8. Buffer control circuitry 34 is responsive to a programmable trigger, such as explicit hint instructions delimiting an instruction burst, or predetermined configuration data specifying parameters of a burst together with a synchronising instruction, to trigger the buffer control circuitry to stall a stallable portion of the processing pipeline (e.g. issue circuitry 16), to accumulate within one or more buffers 30, 32 fetched instructions starting from a predetermined starting instruction, and, when those instructions have been accumulated, to restart the stallable portion of the pipeline.