Programmable High-Speed Interface for Lane-to-Lane Skew Sync
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Solution Overview
Problem
Current serializer-deserializer to framer interfaces, such as SFI-4.02, are constrained in meeting high data rates of approximately 10 Gb/s while maintaining lane-to-lane skew within specified limits, limiting their implementation to Application Specific Integrated Circuits (ASICs) which have slower time to market and higher costs compared to Field Programmable Gate Arrays (FPGAs).
Innovation Solution
A high-speed interface in a programmable logic device utilizing multi-gigabit transceivers with locked-loop circuitry, data rate converters, and skew synchronization blocks to provide transmit and receive clock signals with different frequencies, and adjust synchronous operation to maintain lane-to-lane skew within a target range, enabling compatibility with SFI-4.02 specifications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If SFI-4.02 specification is implemented in ASICs, then lane-to-lane skew constraint is met, but time to market increases and cost increases
Solution Approach 1:
The patent copies the SFI-4.02 interface functionality from ASIC implementations into a reconfigurable logic device, achieving the same lane-to-lane skew control (±10 bits) through programmable logic elements including MGTs, data rate converters, and skew synchronization blocks, thereby avoiding ASIC manufacturing lead times while meeting the specification requirements
Solution Approach 2:
The patent changes the implementation parameters by using reconfigurable logic devices instead of fixed ASIC architecture, allowing the same SFI-4.02 functionality to be achieved with different hardware platforms that offer faster time-to-market and lower cost for lower volume applications
2Manufacturing precision
If SFI-4.02 specification is implemented in ASICs, then lane-to-lane skew constraint is met, but cost increases for lower volume applications
Solution Approach 1:
The patent replicates the SFI-4.02 interface functionality in reconfigurable logic devices, achieving identical lane-to-lane skew control performance without incurring ASIC development and manufacturing costs, making it economically viable for lower volume applications
Solution Approach 2:
The patent uses a universal reconfigurable logic device platform that can implement SFI-4.02 interfaces along with other functionalities, eliminating the need for dedicated ASIC designs and reducing costs through shared hardware resources and programmable architecture
3Manufacturing precision
If multi-gigabit transceivers provide clock signals with different frequencies, then lane-to-lane skew is maintained within target range, but device complexity increases
Solution Approach 1:
The patent introduces intermediary components including data rate converters and skew synchronization blocks that mediate between multi-gigabit transceivers operating at different frequencies, converting and synchronizing clock signals to maintain lane-to-lane skew within ±10 bits while managing the complexity through structured intermediate processing stages
Data Source
AI summary
A high-speed interface for implementation in a programmable device such as, e.g., a programmable logic device (“PLD”) is described. Multi-gigabit transceivers of the PLD provide transmit and receive lock signals and have inputs for reference transmit and receive clock signals. One of the multi-gigabit transceivers provides a first transmit clock signal, a first receive clock signal, and a second receive clock signal. A data rate converter fractionally multiplies a second transmit clock signal to provide the reference transmit clock signal. A skew synchronization block obtains respective transmit and receive lock signals from the multi-gigabit transceivers and provides respective receive and transmit synch adjustment signals to the multi-gigabit transceivers. Synchronous operation of the multi-gigabit transceivers in receive and transmit directions is adjusted with receive and transmit synch adjustment signals to maintain lane-to-lane skew for the high-speed interface within a target range.