Programmable Interrupt Controller for Low-Latency Graph Pipelines

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Solution Overview

Problem

Conventional processor architectures face inefficiencies and scalability challenges in handling graph analytics due to sparse graph structures, leading to poor resource usage, cache thrashing, and high latency in memory access, which limits the performance of graph processing workloads.

Innovation Solution

A specialized graph processing core architecture with multi-threaded pipelines, optimized memory access, and a hardware-based Interrupt Controller Unit (ICU) to manage interrupts efficiently, enabling low latency and high bandwidth for graph processing tasks.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional processor architectures are used for graph analytics, then general-purpose computing is achieved, but memory latency increases and resource utilization deteriorates

Engineering Contradiction:

Improvememory latencyVSAvoidgraph processing performance

Core Design Contradiction:

Loss of timeVSProductivity

Solution Approach 1:

The system segments graph processing workloads into compute operations and memory access operations, executing them on specialized hardware units rather than general-purpose processors. This segmentation allows memory-intensive graph analytics to bypass conventional CPU memory bottlenecks by accessing optimized memory structures directly through the interrupt controller unit and associated memory interfaces.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The interrupt controller unit serves as an intermediary between I/O devices and multi-threaded pipelines, providing low-latency interrupt delivery mechanisms that bridge the gap between external events and graph processing threads. This intermediary structure enables efficient context switching and thread management without the overhead of conventional processor interrupt handling.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Loss of time

If conventional interrupt handling mechanisms are used, then system compatibility is maintained, but interrupt latency increases

Engineering Contradiction:

Improveinterrupt latencyVSAvoidinterrupt handling efficiency

Core Design Contradiction:

Loss of timeVSEase of operation

Solution Approach 1:

The system performs preliminary actions by pre-configuring interrupt vectors, priority levels, and thread affinity mappings in hardware registers before interrupt events occur. The interrupt controller unit maintains ready-to-execute interrupt handling pathways, allowing immediate response to I/O events without the software configuration overhead present in conventional systems.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The interrupt controller implements dynamic interrupt routing that adapts to real-time system conditions, allowing interrupt priorities and target thread selections to change based on current workload states. This dynamic behavior enables efficient load balancing and priority management while maintaining deterministic interrupt response times.

Inventive Principle:

Principle #15Dynamics

3Productivity

If multi-threaded pipelines are implemented, then processing throughput increases, but synchronization complexity increases

Engineering Contradiction:

Improveprocessing throughputVSAvoidsynchronization complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Each multi-threaded pipeline maintains self-service synchronization capabilities through dedicated hardware registers and control mechanisms within the interrupt controller unit. Threads can independently manage their own interrupt masks, priority levels, and state information without requiring complex external synchronization protocols, reducing overall system synchronization complexity.

Inventive Principle:

Principle #25Self-service

4Productivity

If specialized graph processing hardware is used, then graph analytics performance improves, but device complexity increases

Engineering Contradiction:

Improvegraph analytics performanceVSAvoidarchitecture complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The interrupt controller unit and multi-threaded pipeline architecture provide universal functionality that serves both graph processing workloads and general-purpose computing tasks. The same hardware structures handle diverse computational patterns, I/O operations, and memory management functions, reducing the need for specialized dedicated hardware for each function while maintaining high graph analytics performance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS12554906B2Low latency and highly programmable interrupt controller unit

Publication Date: 2026.02.17 INTEL CORP

AI summary

A graph processing core includes a plurality of processing pipelines and an interrupt controller unit. Each processing pipeline executes one or more threads and includes, for each thread, a register indicating a currently executing program counter vector and another register indicating an interrupt or exception handler vector. The interrupt controller unit may receive interrupt or exception notifications from the processing pipelines, determine a handler vector based on the notification and a set of registers of the interrupt controller unit, and transmit the handler vector to the processing pipeline that issued the interrupt or exception notification. Further, the issuing pipeline may receive the handler vector from the interrupt controller unit, write a value in the first register into the second register, write the handler vector into the first register, and invoke an interrupt or exception hander based on the value written into the first register.