Multi-Mode Programmable IO Circuit for High-Speed EOS Protection

Solution Overview

Problem

Programmable logic devices face challenges with thin-gate transistors failing due to high input voltages, while thick-gate transistors cannot support higher speeds, and existing solutions fail to provide efficient bandwidth and electrical overstress protection.

Innovation Solution

Implementing a heterogeneous mix of high-speed, EOS-protected multiplexers and variable supply multiplexers using thin-gate transistors to support various IO standards, enabling higher speeds and cost-effective fabrication with reduced component count.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If thin-gate transistors are used to support higher speeds, then speed is improved, but reliability deteriorates due to failure under high input voltages

Engineering Contradiction:

Improvetransistor speedVSAvoidtransistor reliability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The patent applies local quality by using different transistor gate thicknesses in different locations within the circuit. Thin-gate transistors are used in high-speed paths where speed is critical, while thick-gate transistors are used in paths that require voltage tolerance. This spatial differentiation allows each location to have the optimal transistor characteristics for its specific function, resolving the contradiction between speed and reliability.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The circuit is segmented into multiple paths with different transistor characteristics. The patent divides the signal routing into high-speed paths (using thin-gate transistors) and high-voltage tolerant paths (using thick-gate transistors). This segmentation allows the system to simultaneously achieve high speed where needed and high reliability where voltage tolerance is required, without requiring a compromise in either direction.

Inventive Principle:

Principle #1Segmentation

2Reliability

If thick-gate transistors are used to protect against high input voltages, then reliability is improved, but speed deteriorates due to limitations of thicker gates

Engineering Contradiction:

Improvetransistor reliabilityVSAvoidtransistor speed

Core Design Contradiction:

ReliabilityVSSpeed

Solution Approach 1:

The patent applies local quality by using different transistor gate thicknesses in different locations within the circuit. Thin-gate transistors are used in high-speed paths where speed is critical, while thick-gate transistors are used in paths that require voltage tolerance. This spatial differentiation allows each location to have the optimal transistor characteristics for its specific function, resolving the contradiction between speed and reliability.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The circuit is segmented into multiple paths with different transistor characteristics. The patent divides the signal routing into high-speed paths (using thin-gate transistors) and high-voltage tolerant paths (using thick-gate transistors). This segmentation allows the system to simultaneously achieve high speed where needed and high reliability where voltage tolerance is required, without requiring a compromise in either direction.

Inventive Principle:

Principle #1Segmentation

3Speed

If a heterogeneous mix of multiplexers is used to provide EOS protection and high speed, then bandwidth is improved, but device complexity increases

Engineering Contradiction:

ImprovebandwidthVSAvoidmultiplexer complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent applies universality by designing multiplexers that can handle multiple functions within a single device. The multiplexers are configured to simultaneously provide signal routing, electrical overstress protection, and bandwidth optimization. This multi-functionality reduces the need for separate dedicated components for each function, thereby managing complexity while achieving high performance.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent applies parameter changes by configuring the heterogeneous mix of multiplexers with different operational parameters optimized for specific functions. Some multiplexers are configured for maximum speed with corresponding control parameters, while others are configured for voltage protection with different parameters. This parameter differentiation allows each multiplexer to operate optimally for its intended purpose while maintaining overall system manageability.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20260031819A1Systems and Methods for a Multi-Mode Programmable IO

Publication Date: 2026.01.29 ALTERA CORP

AI summary

Systems or methods of the present disclosure may provide an integrated circuit system that includes a programmable logic device that includes programmable logic units implementing a user design and programmable input/output (IO) circuitry including multiple receiver instances that include a first type of multiplexer to receive a pad input, a second type of multiplexer to receive a voltage, and a third type of multiplexer to receive a clock. The first type of multiplexer is a high-speed multiplexer that has electrical overstress (EOS) protection, the second type of multiplexer has EOS protection and responds slower than the first type of multiplexer, and the third type of multiplexer does not have EOS protection. The programmable IO circuitry also includes a receiver to selectively receive outputs of the first type of multiplexer, the second type of multiplexer, and the third type of multiplexer at an input of the receiver.