Programmable Latency Circuits for Multiprocessor Ring Bus Timing
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Solution Overview
Problem
In multiprocessing systems, the unpredictable latency pattern due to faulty sub-processors in integrated circuits (ICs) leads to undesirable timing problems, as the location of faulty sub-processors is unpredictable, affecting data transfer latency between sub-processors connected via a ring bus.
Innovation Solution
Implementing programmable latency circuits using flip flops in each sub-processor to adjust data transfer delays, ensuring a predictable latency pattern by defining and altering delay patterns based on the location of disabled sub-processors, thereby maintaining consistent latency across the system.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If redundant circuits are used to replace faulty components, then IC yield is improved, but latency pattern predictability deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing alternative latency patterns in lookup tables during manufacturing. When a faulty sub-processor is detected, the system retrieves the pre-computed latency pattern corresponding to that specific fault configuration, eliminating the need for real-time calculation and ensuring predictable latency despite the fault.
Solution Approach 2:
The patent changes the latency parameter dynamically based on the fault configuration. By adjusting latency values according to which sub-processor is faulty and its position in the ring bus, the system maintains predictable timing characteristics. This is achieved through selecting from multiple pre-defined latency patterns stored in lookup tables.
2Reliability
If sub-processors are disabled to handle faults, then system reliability is improved, but data transfer latency becomes unpredictable
Solution Approach 1:
The patent implements feedback by having the system detect which sub-processor is faulty and use that information to select the appropriate latency pattern from lookup tables. This closed-loop approach ensures that the latency characteristics adapt to the actual system state, maintaining predictability despite dynamic fault conditions.
Solution Approach 2:
The patent prepares multiple latency patterns in advance during system design and manufacturing. When a fault occurs, the system simply retrieves the pre-computed pattern matching the fault configuration, avoiding real-time latency calculation and ensuring immediate, predictable timing behavior.
3Manufacturing precision
If latency patterns are adjusted for faulty sub-processors, then timing predictability is improved, but system complexity increases
Solution Approach 1:
The patent uses copying by creating lookup tables that store pre-computed latency patterns for different fault configurations. Instead of implementing complex real-time calculation logic, the system copies the appropriate pre-calculated pattern from the lookup table based on the detected fault, significantly reducing computational complexity while maintaining timing predictability.
Solution Approach 2:
The patent performs the complex latency calculation work in advance during system design and manufacturing, storing the results in lookup tables. This shifts the complexity from runtime operation to preliminary setup, making the runtime system simpler while ensuring accurate timing predictability when faults occur.
Data Source
AI summary
Methods and apparatus provide for a multiprocessor system including: a plurality of sub-processors operatively coupled to one another over a ring bus, whereby data may be transmitted over one or more paths on the ring bus between pairs of the sub-processors; and a plurality of programmable delay circuits, each associated with at least one of the sub-processors, and each being operable to alter a delay of data transfer at least one of into and out of its associated sub-processor in order to alter one or more latencies associated with the paths on the ring bus between pairs of the sub-processors.