Programmable Latency Count for Multi-Chip Memory Bandwidth
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Solution Overview
Problem
Multi-chip memory systems experience reduced memory bandwidth due to initial access times when switching between memory devices, leading to delays and inefficiencies in data access across multiple memory layers.
Innovation Solution
Programming the initial access times for memory devices such that the access time for a second memory device coincides with or exceeds the access time for the first memory device plus the time required to read data from the first memory device, allowing for concurrent or reduced waiting periods between read operations across multiple memory layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a wide shared bus is used to read data from multiple memory devices, then data access from individual memory devices is fast, but memory bandwidth is reduced due to initial access delays when switching between memory devices
Solution Approach 1:
The host controller pre-programs different initial access times for each memory device in the bank. This preliminary configuration allows memory devices to be accessed in an overlapping manner, where the next memory device begins its access cycle before the previous one completes, thereby eliminating idle waiting periods and improving overall memory bandwidth
Solution Approach 2:
The system dynamically adjusts the initial access time for each memory device based on its position in the access sequence. By making the access times dynamic and device-specific rather than uniform, the system optimizes the timing of each memory access to achieve continuous data flow and maximize bandwidth utilization
Data Source
AI summary
Disclosed herein are system, method and/or computer program product embodiments for increasing memory bandwidth when accessing a plurality of memory devices. An embodiment operates by executing, by at least one processor, a first read operation to read data from a first memory device following an access time for the first memory device. The embodiment further includes executing, by the at least one processor, a second read operation to read data from a second memory device following an access time for the second memory device. The access time for the second memory device is substantially the same or longer than the access time for the first memory device plus a time it takes to read data from the first memory device.