Programmable LDPC Decoder for Reconfigurable Parity-Check Matrices
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Solution Overview
Problem
Existing LDPC decoders are often preconfigured to support only a limited number of LDPC codes, making them inflexible as new communication standards emerge and older codes are phased out, necessitating a programmable solution that can dynamically configure and reconfigure to support a wide range of LDPC codes.
Innovation Solution
A programmable LDPC decoder circuit comprising an LDPC repository, an LDPC code configurator, and LDPC decoding circuitry that stores and updates parity-check information for various LDPC codes, allowing for iterative decoding of codewords using shared and reusable parity-check information, enabling support for multiple LDPC codes, including quasi-cyclic codes with circulant sub-matrices of varying sizes and weights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If existing LDPC decoders are preconfigured to support only a limited number of LDPC codes, then device complexity is reduced and manufacturing is easier, but adaptability to different communication standards deteriorates
Solution Approach 1:
The decoder is designed with a universal configuration mechanism that can support multiple LDPC codes through a single programmable interface. The configuration register and control logic enable the same hardware to be reconfigured for different codes without requiring multiple dedicated decoder circuits, thus achieving multi-functionality while controlling complexity.
Solution Approach 2:
The decoder incorporates dynamic reconfiguration capability through configurable parameters such as circulant size, number of layers, and iteration count. These parameters can be dynamically adjusted via the configuration register to adapt to different communication standards and code requirements, transforming a static decoder into a dynamic, adaptable system.
2Adaptability or versatility
If the number of cycles needed to process an entire layer of a base matrix is increased to support more codes, then adaptability improves, but processing speed deteriorates
Solution Approach 1:
The decoder utilizes parameter changes to optimize performance for different codes. By adjusting parameters such as the number of iterations, circulant size, and layer configuration through the configuration register, the decoder can achieve both high adaptability and maintained processing speed. The system selects optimal parameter combinations based on the specific code being decoded.
Solution Approach 2:
The configuration register pre-stores optimal decoding parameters for multiple LDPC codes. Before decoding begins, the appropriate configuration is loaded into the register, allowing the decoder to quickly switch between codes without runtime reconfiguration overhead. This preliminary setup enables both flexibility and speed.
3Productivity
If hardware resources are increased to support more parallel processing of layers, then productivity increases, but device complexity worsens
Solution Approach 1:
The base matrix is segmented into multiple layers that can be processed in parallel. The configuration register controls the number of layers and their respective parameters, allowing the decoder to divide the decoding task into manageable parallel segments. This segmentation enables high productivity without requiring a monolithic complex hardware structure.
Solution Approach 2:
The decoder exploits the layer dimension of the base matrix to achieve parallel processing. By organizing the decoding process across multiple layers (an additional dimension beyond simple row processing), the system increases productivity through parallelism while maintaining manageable hardware complexity through structured layer management.
Data Source
AI summary
A decoder circuit includes a low-density parity-check (LDPC) repository, an LDPC code configurator, and LDPC decoding circuitry. The LDPC repository stores parity-check information associated with one or more LDPC codes. The LDPC code configurator may receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and may update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The LDPC decoding circuitry may receive a first codeword encoded in accordance with the LDPC code. More specifically, the LDPC decoding circuitry may be configured to read the parity-check information associated with the first LDPC code from the LDPC repository and iteratively decode the first codeword using the parity-check information associated with the first LDPC code.