Programmable LDPC Decoder for Shared Encoding and Decoding
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Solution Overview
Problem
Existing LDPC decoders are preconfigured to support only a limited number of LDPC codes, making them inflexible as new communication standards emerge, and they often require separate hardware for encoding and decoding, which is inefficient.
Innovation Solution
A programmable LDPC decoder with a repository for storing parity-check information and configurable LDPC decoder circuitry that can dynamically switch between LDPC encoding and decoding based on control signals, allowing it to support a wide range of LDPC codes and share resources for both operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If existing LDPC decoders are preconfigured to support only a limited number of LDPC codes, then the hardware structure is simplified and easier to manufacture, but the adaptability to different LDPC codes and standards is reduced
Solution Approach 1:
The decoder is designed with a universal architecture that can perform both LDPC decoding and encoding operations using the same hardware resources. The decoder circuitry can be configured through control signals to operate in decoding mode or encoding mode, allowing a single device to serve multiple functions and support various LDPC codes without requiring separate dedicated hardware for each code type.
Solution Approach 2:
The decoder incorporates reconfigurable circuitry that can dynamically change its operation mode between decoding and encoding based on control signals. This dynamic reconfiguration capability allows the hardware to adapt to different LDPC codes and standards by loading appropriate parity-check matrices and adjusting operational parameters, thereby improving versatility while maintaining a relatively simple base hardware structure.
2Reliability
If separate hardware is used for LDPC encoding and decoding, then each function can be optimized independently, but the hardware requirements and device complexity increase
Solution Approach 1:
The patent merges the LDPC decoding and encoding functions into a single unified hardware device. The same decoder circuitry, memory structures, and control logic are used for both decoding incoming codewords and encoding outgoing data blocks. This consolidation reduces the overall hardware requirements and device complexity while maintaining the ability to perform both functions with optimized algorithms through software/control signal configuration.
Solution Approach 2:
The unified decoder is designed to perform multiple functions including LDPC decoding, LDPC encoding, and supporting various LDPC code standards. By making the hardware universal and multi-functional, the system achieves function optimization through configurable algorithms while avoiding the increased complexity that would result from having separate dedicated hardware for each function.
3Adaptability or versatility
If a decoder supports a wide range of LDPC codes through reconfiguration, then adaptability is improved, but the configuration complexity and setup time increase
Solution Approach 1:
The system includes pre-configured parity-check matrices and code specifications stored in memory for multiple LDPC codes and standards. When a specific LDPC code needs to be supported, the corresponding pre-stored configuration data is loaded into the decoder, eliminating the need for complex real-time configuration. This preliminary preparation of configuration data reduces setup time and configuration complexity while maintaining high adaptability to different codes.
Solution Approach 2:
The patent introduces an intermediary configuration interface that manages the loading and switching of different LDPC code specifications. This intermediary layer handles the complexity of configuration by providing a simplified interface for selecting and loading appropriate parity-check matrices and code parameters, thereby reducing the perceived configuration complexity for users while supporting a wide range of LDPC codes.
4Productivity
If the same hardware is used for both encoding and decoding, then hardware efficiency is improved, but the processing time for switching between operations may increase
Solution Approach 1:
The decoder employs dynamic reconfiguration capabilities that allow rapid switching between encoding and decoding operations through control signals. The hardware is designed to maintain readiness for mode switching by keeping essential computational units and memory structures in a state that can be quickly activated for either operation, minimizing the time penalty associated with mode transitions while maximizing hardware efficiency through resource sharing.
Data Source
AI summary
A decoder circuit includes a low-density parity-check (LDPC) repository to store parity-check information associated with one or more LDPC codes and an LDPC code configurator to receive a first LDPC configuration describing a parity-check matrix for a first LDPC code and to update the parity-check information in the LDPC repository to reflect the parity-check matrix for the first LDPC code. The decoder circuit further includes an LDPC decoder circuitry configurable, based on control signals, to perform LDPC decoding of codewords or LDPC encoding of information using the parity-check information from the LDPC repository.