Programmable LDPC Decoder for Variable Codeword Lengths
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing LDPC decoders face challenges in reducing hardware implementation costs and flexibility, particularly in decoding codewords of different lengths and code structures, with existing methods being inflexible and costly for large block lengths.
Innovation Solution
The implementation of a programmable LDPC decoder that uses a lifting factor Z=K×N, allowing for parallelism N to match required throughput, which reduces hardware complexity while supporting decoding of different codeword sizes and code structures through vectorized message passing and permutation-based processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a programmable LDPC decoder with lifting factor Z=K×N is implemented, then hardware complexity is reduced and flexibility is improved, but device complexity increases due to the need for programmable control structures
Solution Approach 1:
The patent implements a programmable LDPC decoder where the lifting factor Z is dynamically configurable as Z=K×N, allowing the hardware to adapt to different code structures and block lengths. This dynamic configuration enables the same hardware architecture to handle multiple LDPC code variants by changing control parameters rather than requiring separate dedicated hardware for each code type, thereby reducing overall hardware complexity while maintaining flexibility.
Solution Approach 2:
The patent utilizes parameter changes by allowing the lifting factor Z and its components K and N to be programmably adjusted. This enables the decoder to optimize its operation for different throughput requirements and code structures by modifying these parameters without changing the physical hardware architecture, resolving the contradiction between hardware complexity and flexibility.
2Productivity
If parallelism N is increased to match required throughput, then productivity is improved, but device complexity increases due to additional parallel processing units
Solution Approach 1:
The patent segments the parallelism factor into two components: Z=K×N, where K represents the number of parallel processing units and N represents the lifting factor for each unit. This segmentation allows independent optimization of throughput (controlled by K) and hardware complexity (controlled by N), enabling system designers to balance these competing requirements based on specific application needs.
Solution Approach 2:
The patent creates a universal decoder architecture that can achieve different throughput levels by programmatically adjusting the lifting factor Z and its components K and N. This multi-functional capability allows the same hardware structure to serve multiple throughput requirements, reducing the need for multiple specialized hardware implementations and thereby reducing overall device complexity.
3Ease of operation
If vectorized message passing and permutation-based processing are implemented, then ease of operation is improved, but device complexity increases due to additional control mechanisms
Solution Approach 1:
The patent replaces complex mechanical control mechanisms with software-based vectorized message passing and permutation-based processing. This substitution allows sophisticated decoding operations to be performed through programmable instructions rather than hardwired control logic, improving ease of operation while managing device complexity through the use of flexible software control.
Solution Approach 2:
The patent introduces vectorized message passing as an intermediary mechanism that simplifies the control flow between processing units. This intermediary layer abstracts the complexity of coordinating multiple parallel units, making the system easier to operate while the underlying control structure handles the complexity of synchronization and data flow management.
Data Source
AI summary
A flexible and relatively hardware efficient LDPC decoder is described. The decoder can be implemented with a level of parallelism which is less than the full parallelism of the code structure used to control the decoding process. Each command of a relatively simple control code used to describe the code structure can be stored and executed multiple times to complete the decoding of a codeword. Different codeword lengths are supported using the same set of control code instructions but with the code being implemented a different number of times depending on the codeword length. The decoder can switch between decoding codewords of different lengths, without the need to change the stored code description information, by simply changing a code lifting factor that is indicative of codeword length and is used to control the decoding process. When decoding codewords shorter than the maximum supported codeword length some block storage locations may go unused.