Programmable Universal Logic Gate for IC Camouflage
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Solution Overview
Problem
Existing methods for protecting integrated circuits against reverse engineering are either too expensive for mass production or incur significant area, energy, and delay penalties, and there is a need for effective techniques to prevent IC piracy and design theft.
Innovation Solution
A programmable logic circuit that implements a universal gate using a combination of MULTI-AND-NOR and AND-ORAND-NOR gates, controlled by program bits, which can realize various basic Boolean functions, thereby providing circuit camouflage and enhancing security against reverse engineering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional reverse engineering protection methods are used, then circuit security is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent implements a universal gate that can perform multiple Boolean functions (AND, OR, NAND, NOR, XOR, XNOR, NOT, BUFFER) by configuring control bits, replacing the need for multiple separate gates. This multi-functional approach reduces circuit area and complexity while maintaining security against reverse engineering, providing a cost-effective solution that does not require expensive specialized protection circuits.
Solution Approach 2:
The patent uses dynamically reconfigurable logic where the gate functionality changes based on control bit values. The circuit can switch between different Boolean functions at runtime, making reverse engineering difficult because the circuit behavior is not fixed. This dynamic reconfiguration capability provides strong security protection while using standard, cost-effective manufacturing processes.
2Reliability
If circuit camouflage techniques are used, then reverse engineering resistance is improved, but area overhead increases
Solution Approach 1:
By implementing a single universal gate that can emulate eight different basic gates through control bit configuration, the patent achieves circuit camouflage without significant area overhead. The same physical hardware structure provides multiple logical functions, reducing the total area required compared to implementing separate camouflage circuits for each gate type.
Solution Approach 2:
The patent merges multiple gate functions into a single reconfigurable logic unit. Instead of having separate physical structures for AND, OR, NAND, NOR, XOR, XNOR, NOT, and BUFFER gates, all these functions are combined into one universal gate structure that can be programmed to perform any of them, significantly reducing area overhead.
3Adaptability or versatility
If multiple separate gates are used to implement Boolean functions, then functional versatility is improved, but device complexity increases
Solution Approach 1:
The patent implements a universal gate that can perform eight different Boolean functions (AND, OR, NAND, NOR, XOR, XNOR, NOT, BUFFER) by configuring four control bits, replacing the need for multiple separate gates. This multi-functional approach reduces circuit area and complexity while maintaining security against reverse engineering.
4Ease of manufacture
If fixed logic circuits are used, then manufacturing simplicity is improved, but adaptability to different functions deteriorates
Solution Approach 1:
The patent uses dynamically reconfigurable logic where the gate functionality changes based on control bit values. The circuit can switch between different Boolean functions at runtime, making reverse engineering difficult because the circuit behavior is not fixed. This dynamic reconfiguration capability provides strong security protection while using standard, cost-effective manufacturing processes.
Data Source
AI summary
According to an embodiment, a programmable logic circuit is described comprising a first data bit input to receive a first data bit a and a second data bit input to receive a second data bit b, a first program bit input to receive a first program bit p1, a second program bit input to receive a second program bit p2, a third program bit input to receive a third program bit p3 and a fourth program bit to receive a fourth program bit p4 and an output configured to output(((a⋀b)⋁(p1⋀a)⋁(p2⋀b))_⋀(p3⋁b⋁a))⋁(a⋀b⋀p4)_.