Programmable Logic Region Configuration via Parallel NoC Routing
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Solution Overview
Problem
Existing programmable integrated circuits, such as FPGAs, face challenges in configuring programmable logic regions due to low bandwidth and serial connections, which hinder parallel processing and result in slow configuration times, especially in virtualized computing environments where frequent reconfiguration is necessary.
Innovation Solution
The integration of a programmable network, like a Network-on-Chip (NoC), enables high-speed communication and parallel processing by segmenting configuration data delivery through multiple configuration frame drivers, allowing for faster configuration of programmable logic regions and supporting out-of-order configuration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional serial configuration methods are used, then device complexity is reduced, but configuration speed deteriorates
Solution Approach 1:
The configuration architecture is segmented into multiple parallel configuration frame drivers (CFDs) that can simultaneously transmit configuration data to different regions of the programmable logic device. This segmentation enables parallel configuration operations, dramatically increasing configuration speed from serial to parallel processing without requiring fundamental changes to the configuration protocol itself.
Solution Approach 2:
The invention transitions from a single-dimension serial configuration approach to a multi-dimensional parallel configuration architecture by introducing multiple CFDs operating simultaneously. This dimensional expansion allows configuration data to flow through multiple channels at once, achieving speedup proportional to the number of parallel channels while maintaining protocol compatibility.
2Productivity
If parallel processing is implemented, then configuration speed improves, but bandwidth requirements increase
Solution Approach 1:
The configuration bandwidth is segmented into multiple dedicated channels, each handled by a separate configuration frame driver. This segmentation distributes the total bandwidth requirement across multiple parallel paths, allowing the system to achieve high throughput without requiring any single channel to carry excessive data loads, thus balancing bandwidth distribution efficiently.
3Adaptability or versatility
If frequent reconfiguration is performed, then adaptability improves, but downtime increases
Solution Approach 1:
The system prepares configuration data in advance and loads it into configuration memory before actual reconfiguration is needed. This preliminary action allows the configuration data to be staged and ready, so when reconfiguration is triggered, the parallel configuration engines can immediately begin processing without waiting for data preparation, thus minimizing downtime while maintaining high adaptability.
Data Source
AI summary
Examples described herein provide for an integrated circuit (IC) having a programmable logic region that is capable of being configured via a programmable network. In an example, an IC includes a programmable logic region, a controller, and a programmable network. The programmable network is connected between the controller and the programmable logic region. The controller is programmed to configure the programmable logic region via the programmable network. In some examples, the programmable logic region can be configured faster, among other benefits.