Programmable Logic Power Domains With Selectable Voltage Regulation

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Solution Overview

Problem

Conventional programmable semiconductor devices like FPGAs are less power efficient, limiting their flexibility and efficiency in meeting the demands of high-speed and low-power consumption required for digital communication, AI, IoT, and robotic controls.

Innovation Solution

A semiconductor device with a selectable power regulator that provides multiple power domains by enabling different voltage levels across regions, allowing for flexible operation and power management, enhancing power conservation and efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional programmable semiconductor device is used to provide flexibility and reconfigurability, then adaptability is improved, but power consumption increases

Engineering Contradiction:
ImprovereconfigurabilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The semiconductor device is divided into multiple independently controllable regions or blocks, each with its own power domain. This allows selective activation of only the regions needed for current operations, leaving other regions in a low-power or standby state, thereby reducing overall power consumption while maintaining reconfigurability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The device implements dynamic power management where power domains can be selectively enabled or disabled based on operational requirements. The ability to dynamically reconfigure which regions are active allows the device to adapt its power consumption profile to match the actual computational workload, maintaining flexibility while improving energy efficiency.

Inventive Principle:
Principle #15Dynamics

2Use of energy by moving object

If multiple power domains are implemented to improve power efficiency, then power consumption is reduced, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoiddevice complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The power management architecture uses universal control mechanisms that can manage multiple power domains through standardized interfaces and control logic. This multi-functional approach allows a single power management unit to handle numerous regions, reducing the need for separate control circuits for each domain and thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The power management structure implements a hierarchical or nested organization where higher-level power management functions control multiple lower-level power domains. This nesting allows complex power management capabilities to be achieved through layered control, where simpler sub-units are coordinated by higher-level controllers, managing complexity through structured organization.

Inventive Principle:
Principle #7Nested doll (Nesting)

Data Source

PatentUS11664806B2Method and apparatus for providing multiple power domains to a programmable semiconductor device
Publication Date: 2023.05.30 GOWIN SEMICON CORP LTD
  • US11664806B2 patent drawing
  • US11664806B2 patent drawing
  • US11664806B2 patent drawing

AI summary

A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.