Programmable Logic Toolchain Learning for Faster Place-and-Route
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Solution Overview
Problem
Existing programmable logic device development toolchains face long execution times in the place and route process, particularly when developing large circuits, due to the need for repeated trial and error with constraint changes, which significantly impacts development periods.
Innovation Solution
A learning apparatus and inference apparatus are developed to acquire and utilize learning data, including resource usage rates and timing slack information, to generate a learned model that infers optimal iterative synthesis parameters for successful place and route, utilizing reinforcement learning and unsupervised learning to reduce the number of trials required.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If repeated trial and error is performed to complete place and route, then successful place and route is achieved, but execution time becomes excessively long
Solution Approach 1:
The system performs preliminary analysis of resource usage rate data and timing slack information before the actual place and route execution. By pre-processing these parameters and using machine learning to predict optimal settings, the system prepares constraint conditions in advance, reducing the need for repeated trials during actual place and route operations.
Solution Approach 2:
The system implements a feedback mechanism where resource usage rate data and timing slack information from previous place and route attempts are fed back into the machine learning model. This feedback loop allows the system to learn from past results and continuously improve its predictions, reducing the number of trials needed for successful place and route.
2Manufacturing precision
If constraint conditions are varied repeatedly for trial, then optimal settings are found, but development period is significantly extended
Solution Approach 1:
The system uses machine learning to automatically determine optimal parameter settings for place and route operations. Instead of manual or exhaustive trial-and-error adjustment of constraint conditions, the learning apparatus analyzes resource usage rate data and timing slack information to directly predict optimal parameters, significantly reducing the time required to find optimal settings while maintaining high precision.
Solution Approach 2:
The system replaces the mechanical trial-and-error process with an intelligent system based on machine learning. The learning apparatus substitutes repetitive manual or automated constraint adjustment with a predictive model that directly outputs optimal settings based on analyzed input data, transforming a time-consuming iterative process into a faster computational prediction task.
3Productivity
If traditional place and route processes are used for large circuits, then complete circuit development is achieved, but execution time becomes unacceptably long
Solution Approach 1:
The system extracts and analyzes key parameters (resource usage rate data and timing slack information) from the complex place and route process. By separating these critical factors and using them as input for machine learning prediction, the system focuses computational effort on the most influential parameters, enabling faster determination of optimal settings for large circuits without sacrificing development completeness.
Data Source
AI summary
A data acquisition unit acquires resource usage rate data for each technology of a programmable logic apparatus development toolchain and timing slack information during technology mapping. An inference unit outputs an iterative synthesis parameter for succeeding in place and route from the resource usage rate data for each technology and the timing slack information during the technology mapping that are acquired by the data acquisition unit using a learned model for inferring an iterative synthesis parameter given to the programmable logic apparatus development toolchain for succeeding in the place and route from the resource usage rate data for each technology and the timing slack information during the technology mapping.