Programmable Logic Packet Processing via Hardened Transceiver Preprocessing

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Solution Overview

Problem

Integrated circuits face challenges in absorbing high-capacity communication channels and maintaining deep packet processing at high port rates, particularly in programmable fabrics, which are limited by frequency of operation and unable to manage large flows effectively.

Innovation Solution

Implementing inline hardened packet processing functions in a transceiver subsystem with parser, extractor, and classifier circuitry to preprocess packets, enabling load balancing and efficient routing to multiple pipelines, thereby offloading processing from programmable logic fabric.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If packet processing is performed in programmable logic fabric, then flexibility and adaptability are improved, but frequency of operation and processing speed deteriorate

Engineering Contradiction:

Improvepacket processing flexibilityVSAvoidfrequency of operation

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The packet processing system is segmented into two distinct parts: a hardened transceiver subsystem for high-speed preprocessing and classification, and a programmable logic fabric for flexible but lower-speed processing. This segmentation allows each component to operate at its optimal speed while maintaining overall system flexibility.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The transceiver subsystem acts as an intermediary between the high-capacity communication channel and the programmable logic fabric. It performs preprocessing, parsing, and classification of packets before they reach the programmable fabric, enabling the fabric to operate at lower frequencies while still handling high-capacity channels effectively.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If deep packet processing is maintained in programmable fabric, then processing capability is improved, but ability to manage high port rates deteriorates

Engineering Contradiction:

Improvepacket processing capabilityVSAvoidhigh port rate management

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The transceiver subsystem performs preliminary packet processing actions including parsing, extracting header information, and classification before packets are passed to the programmable logic fabric. This preliminary action reduces the processing burden on the fabric, enabling it to maintain deep processing capabilities while handling high port rates effectively.

Inventive Principle:

Principle #10Preliminary action

3Quantity of substance

If high-capacity communication channel is absorbed by programmable fabric, then communication capacity is improved, but processing efficiency deteriorates

Engineering Contradiction:

Improvecommunication capacityVSAvoidprocessing efficiency

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The system extracts and removes the high-speed packet processing functions from the programmable logic fabric and places them in a dedicated hardened transceiver subsystem. This extraction allows the programmable fabric to focus on flexible processing tasks at lower speeds while the transceiver subsystem handles the high-capacity channel absorption and high-speed preprocessing.

Inventive Principle:

Principle #2Taking out (Extraction)

Data Source

PatentUS20250310263A1Systems and Methods for Packet Processing in Programmable Logic Devices

Publication Date: 2025.10.02 ALTERA CORP

AI summary

Systems or methods of the present disclosure may provide an integrated circuit system, including programmable logic fabric and transceiver circuitry coupled to the programmable logic fabric, wherein the transceiver circuitry includes a parser configurable to parse a packet to identify a number of headers, a number of header offsets, or both, an extractor configurable to extract a number of fields from the number of heads, the number of header offsets, or both, and a classifier configurable to classify the packet to a stream based on the number of fields.