Programmable LUT Switch Architecture for Low-Leakage FPGA Logic
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Solution Overview
Problem
Existing programmable logic devices, particularly field-programmable gate arrays (FPGAs), face challenges with silicon area consumption and power leakage due to the large number of devices required in look-up tables (LUTs), which becomes a limitation in battery-operated applications as process technology scales down.
Innovation Solution
The implementation of programmable logic generators using simple programmable switches that emulate addressable memory units, reducing the number of devices needed and employing programmable memories with higher gate voltages to construct 2- and 3-input LUTs, which can be combined to form larger functions while minimizing power leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional look-up tables with SRAM memory cells and NMOS pass gates are used, then logic functions can be implemented, but silicon area consumption increases and power leakage becomes significant
Solution Approach 1:
The patent merges the memory cell and pass gate functions into a single integrated structure. The programmable logic device combines the lookup table functionality with the switching mechanism, eliminating the need for separate SRAM memory cells and NMOS pass gates. This integration reduces the total device count from 30+ devices per LUT to a compact unified structure, directly addressing the silicon area consumption problem while maintaining full logic function implementation capability
Solution Approach 2:
The patent implements a universal logic module that can perform multiple logic functions through a single reconfigurable structure. The programmable switches and interconnects allow the same hardware to implement various logic functions dynamically, eliminating the need for dedicated circuits for each function. This multi-functionality approach reduces overall silicon area while maintaining adaptability for different logic operations
2Adaptability or versatility
If traditional look-up tables with multiple NMOS and PMOS devices are used, then logic functions can be implemented, but power leakage increases
Solution Approach 1:
The patent extracts and eliminates the problematic NMOS pass gates that cause significant power leakage in traditional LUTs. By removing these leakage-prone components and replacing them with a different switching mechanism, the invention directly addresses power leakage reduction while maintaining logic function implementation through alternative circuit design
Solution Approach 2:
The patent discards the traditional SRAM-based memory cell structure that contributes to power leakage and recovers the essential lookup table functionality through a more efficient implementation. The new design recovers the programmable logic capability without retaining the leakage-prone components, achieving energy efficiency while maintaining adaptability
3Area of moving object
If process technology scales down to reduce device size, then integration density improves, but Vdd voltage scales down causing NMOS pass gates to be ineffective
Solution Approach 1:
The patent changes the operating parameters and circuit topology to accommodate scaled-down process technology. Instead of relying on NMOS pass gates that become ineffective at low Vdd, the invention adopts a different switching mechanism that remains effective at reduced voltages. This parameter change allows the device to function reliably in advanced process nodes while maintaining small device size for high integration density
Data Source
AI summary
Methods and apparatus are disclosed to implement programmable logic generators that provide the advantages of compatible look-up tables (LUTs) while utilizing less silicon real estate and power for the same number of functions. The disclosed methods and apparatus employ programmable switches to emulate memory units that are used in LUTs and illustrate construction of 2- and 3-input LUTs as building blocks of other multi-input LUTs.