Programmable Macro BIST Controller for IC Test Flexibility
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Solution Overview
Problem
Conventional built-in self-test (BIST) engines for integrated circuits lack programmability at the full chip level, limiting their ability to execute arbitrary test programs efficiently and cost-effectively, and do not provide methods for broadcasting soft memory test algorithms or system-level operations like power switching.
Innovation Solution
A programmable macro BIST controller is introduced to control a set of BIST engines, allowing for the reception of test vectors, identification of associated BIST engines, and generation of commands to perform tests, incorporating macro instructions for memory test operations, power control, and conditional branching, which eliminates the need for individually programmable engines and enables system-level operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional BIST engines are used, then testing can be performed, but programmability at the full chip level is limited
Solution Approach 1:
The system is divided into a controller that receives high-level test vectors and multiple BIST engines that execute specific test operations. The controller translates macro instructions into engine-specific commands, allowing each engine to remain relatively simple while the overall system achieves full programmability through the controller's ability to interpret and distribute test vectors across multiple engines.
2Adaptability or versatility
If individually programmable engines are implemented, then test flexibility improves, but die size increases
Solution Approach 1:
Multiple BIST engines share common control logic and instruction decoding resources through the centralized controller. The controller merges the programmability function for all engines, eliminating the need for each engine to have its own complete programmable interface. This allows test flexibility to be achieved while reducing the total die area by sharing control resources across multiple engines.
3Reliability
If more comprehensive test operations are included, then testing capability improves, but engineering effort increases
Solution Approach 1:
The BIST system performs self-testing through automated macro instructions that are loaded and executed by the controller. The system can autonomously configure engines, load test patterns, execute test sequences, and collect results without requiring extensive external engineering intervention. This self-service capability comprehensively tests the system while minimizing ongoing engineering effort.
4Adaptability or versatility
If system-level operations are added, then functionality improves, but device complexity increases
Solution Approach 1:
The controller is designed as a universal interface that can interpret various macro instructions and translate them into appropriate commands for different types of BIST engines. It handles multiple functions including test vector distribution, engine configuration, result collection, and system-level operations like power control. This multi-functionality approach allows comprehensive system-level operations while managing complexity through a standardized control architecture.
Data Source
AI summary
A system and method for using a programmable macro built-in self-test (BIST) to test an integrated circuit. The method includes receiving, by a built-in self-test (BIST) controller of an integrated circuit (IC) device from a testing equipment, a test vector of a first type for testing a first region of the IC device. The method includes identifying, based on the test vector of the first type, a first BIST engine of a plurality of BIST engines associated with the first region of the IC device. The method includes generating, based on the test vector of the first type, a first command of the second type. The method includes configuring, based on the first command of the second type, the first BIST engine of the plurality of BIST engines to cause the first BIST engine to perform a first set of tests on the first region of the IC device.