Programmable Memory Access Mapping for Low-Latency Data Reordering
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Solution Overview
Problem
Existing memory architectures suffer from latency issues due to read/write conflicts and slow memory access, which limit processing speeds in intensive computing tasks like fully homomorphic encryption and optical computing, where data needs to be frequently re-ordered or transposed, leading to bottlenecks.
Innovation Solution
A hybrid memory architecture that allows data to be stored and retrieved discontinuously from arbitrary memory cell locations using state machine controllers and in-memory compute logic, enabling arithmetic and logic operations directly on the memory cells, and utilizing a programmable memory access logic to map data sequences for efficient reordering and transposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If data is stored in RAM organized in rows with traditional read/write operations, then memory access is simplified, but read/write conflicts occur causing latency and reduced processing rates
Solution Approach 1:
The patent segments memory access into cell-level operations rather than row-level operations. Each memory cell can be independently addressed and accessed, allowing fine-grained control over read/write operations. This segmentation enables simultaneous operations on different cells without conflicts, resolving the contradiction between simple row-based access and high processing rates.
Solution Approach 2:
The patent implements dynamic memory addressing where the memory controller can programmatically determine arbitrary cell locations for read/write operations. The system transitions from static row-based access patterns to dynamic cell-level access, allowing optimization of access patterns to avoid conflicts and improve processing rates while maintaining operational simplicity through automated control.
2Speed
If register memories are used for fast data buffering, then access speed is improved, but memory capacity is limited
Solution Approach 1:
The patent creates a hybrid memory architecture that adds a new dimension to memory organization. Instead of choosing between fast small-capacity register memory or slow large-capacity RAM, the system implements cell-level addressability that allows any memory cell to function as a register when needed. This dimensional change in address space enables both fast access and large capacity simultaneously.
Solution Approach 2:
The patent makes all memory cells universal by enabling any cell to be accessed individually like a register, while also allowing the entire array to function as large-capacity storage. The memory controller can programmatically select any cell for fast access operations, making the entire memory array multi-functional - capable of providing both register-like speed and RAM-like capacity.
3Adaptability or versatility
If data needs to be frequently re-ordered or transposed for computing tasks, then computational flexibility is improved, but memory access latency increases
Solution Approach 1:
The patent implements preliminary action by allowing the memory controller to pre-calculate and program optimal access patterns before data operations are needed. The system can anticipate reordering requirements and prepare access sequences in advance, reducing latency during actual data transformation operations. This is particularly useful for predictable computing patterns like Fourier transforms.
Solution Approach 2:
The patent introduces the memory controller as an intermediary that mediates between data storage and computational needs. The controller intelligently manages read/write operations, determining optimal cell access patterns to facilitate data reordering and transposition. This intermediary layer reduces latency by optimizing the coordination between memory access and computational requirements.
Data Source
AI summary
A memory including: an array of memory cells; a memory access logic programmable to generate a write allocation that maps an input comprising elements of data in a first sequence to the memory cells of the array and a read allocation that maps the memory cells of the array to an output comprising elements of data in a second sequence; and a memory controller arranged to write the elements of data at the input to the array based on the write allocation and to read the elements of data stored in the array to the output based on the read allocation.