Programmable Memory Built-In Self-Test for Flexible Testing
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Solution Overview
Problem
Traditional memory unit test procedures are limited in flexibility and cannot be customized by users, failing to adequately stress and detect faults in memory models, particularly as memory density increases in system-on-chip designs, leading to challenges in ensuring memory quality and detecting defects.
Innovation Solution
The implementation of a programmable memory built-in self-test (PMBIST) system that includes a Joint Test Action Group (JTAG) controller and direct access controller, allowing for user-defined test plans and algorithms to be programmed and executed, enabling customizable testing of memory units with minimal hardware overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional predefined testplans are used, then hardware implementation is simple, but test flexibility and customization are limited
Solution Approach 1:
The patent implements dynamic testplan configuration by allowing users to programmably define test algorithms, address orders, and data backgrounds rather than being restricted to fixed predefined testplans. The testplan can be dynamically generated and loaded into the MBIST logic, enabling adaptability to different memory configurations and testing requirements without hardware changes.
Solution Approach 2:
The patent enables parameter changes in test procedures by allowing users to modify test algorithms, address sequences, and data patterns through software configuration. The MBIST system accepts parameterized test plans that can be adjusted based on specific memory defect characteristics, enabling customized testing without physical hardware modifications.
2Reliability
If more test algorithms are added to detect all possible scenarios, then detection capability improves, but hardware area overhead increases
Solution Approach 1:
The patent uses copying by implementing a programmable MBIST system where test algorithms are stored as software routines rather than hardwired hardware circuits. Multiple test algorithms can be loaded into the same MBIST logic block, effectively copying test functionality through software rather than duplicating hardware, thus maintaining low area overhead while providing comprehensive testing capability.
Solution Approach 2:
The patent implements universality by designing a single MBIST logic structure that can execute multiple different test algorithms through programmable configuration. The same hardware resource serves multiple testing functions by loading different test plans, eliminating the need for separate dedicated hardware circuits for each test algorithm and minimizing area overhead.
3Measurement precision
If test procedures are made more comprehensive to stress memory models, then detection precision improves, but power consumption increases
Solution Approach 1:
The patent applies periodic action by implementing test algorithms that systematically vary read and write operation patterns over time. The testplan can schedule different stress testing sequences at different phases, allowing comprehensive memory stress testing while controlling power consumption through time-multiplexed testing rather than continuous high-power operations.
Solution Approach 2:
The patent uses partial action by allowing users to select and execute only the specific test algorithms and stress patterns needed for their particular memory defect detection requirements, rather than running all possible comprehensive tests. This enables sufficient detection precision for identified issues while minimizing unnecessary power consumption from exhaustive testing.
Data Source
AI summary
An exemplary memory arrangement can be provided, which can include, for example, a memory(ies), and an algorithmic memory unit(s) (AMU) coupled to the memory(ies), wherein the AMU includes a programmed testplan algorithm(s) configured to test the memory(ies). The AMU(s) can further include a hardwired testplan(s) configured to test the memory(ies). A Joint Test Action Group (“JTAG”) controller may be coupled to the AMU(s), which can be configured to access logic of the programmed testplan algorithm(s). A direct access controller (DAC) can be coupled to the AMU(s), which can be configured to access internal nodes in the AMU(s). The DAC can be configured to activate the programmed testplan algorithm(s) using a minimally direct access pin interface in the AMU(s).