Programmable Memory Cell Structure Without Extra Masking Steps
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Solution Overview
Problem
Existing memory technologies fail to address the need for adaptable and cost-effective programmable memory cells suitable for various circuits without requiring additional masking steps.
Innovation Solution
A programmable memory cell design comprising a semiconductor substrate with insulated conductive walls, a first conductivity type and a second conductivity type, and a second conductivity type, and a second conductivity type, with capacitive coupling ratios and electrical fields applied to program and sense values, utilizing MOSFET transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory cells are adapted to different technologies, then versatility is improved, but manufacturing complexity increases due to additional masking steps
Solution Approach 1:
The memory cell design uses a universal structure with a semiconductor substrate, insulated conductive walls, and doped regions that can be programmed through electrical field application. This multi-functional design allows the same cell structure to be adapted to different circuit technologies (P-type and N-type conductivity) without requiring additional masking steps, resolving the contradiction between versatility and manufacturing complexity
2Ease of operation
If programming is achieved through electrical field application, then ease of operation is improved, but energy consumption increases
Solution Approach 1:
The patent employs controlled parameter changes in the electrical field (applying fields between 5 MV/cm and 10 MV/cm) to program the memory cell. By optimizing the electrical field strength within this specific range, the invention achieves effective programming operation while minimizing energy consumption, balancing ease of operation with energy efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables adaptable programmable memory cells suitable for various circuits using existing MOSFET transistor manufacturing processes without additional masking steps, allowing programming and sensing with low voltages.
Implementation Method 1
programming a first value into the memory cell by applying an electrical field comprised between 5 MV/cm and 10 MV/cm between the first region and the second layer
Implementation Method 2
programming a second value into the memory cell by applying an electrical field comprised between 5 MV/cm and 10 MV/cm between the third region and the second layer
Implementation Method 3
the second region comprising second top parts, the second top parts forming a transistor with the first and second layers
Data Source
AI summary
A memory cell includes first, second, and third semiconductor regions laterally bounded by insulated conductive walls; a first insulating layer overlaying the first, second, and third semiconductor regions; and a second conductive layer disposed facing a part of each of first, second, and third semiconductor regions. A first top part of the first semiconductor region is first conductivity type doped and faces the second conductive layer. The second semiconductor region includes second top parts forming a transistor with the first insulating layer and second conductive layer. A third top part of the third semiconductor region is second conductivity type doped and faces the second conductive layer. To program the memory cell, an electrical field is applied between the first semiconductor region and the second conductive layer and electrical field is applied between the third semiconductor region and the second conductive layer.