Programmable Memory Cell Using Resistive Switching Element
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Solution Overview
Problem
Current memory technologies face challenges in achieving fast access speeds, low energy consumption, and integration with CMOS while storing non-volatile data, as volatile memory cells lose data when power is removed and non-volatile memory cells like flash memory are slow and have high supply voltage requirements.
Innovation Solution
A memory device with a configuration of transistors and resistance switching elements that allows for non-volatile data storage using programmable resistive states, enabling quick data transfer to volatile storage nodes, and independent programming of resistance elements for efficient data storage and retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory cells (SRAM) are used for fast access, then access speed is improved, but data is lost when power is removed
Solution Approach 1:
The memory cell is segmented into two functional parts: a volatile SRAM latch for fast data access and a non-volatile resistance switching element for data retention. The latch circuit (comprising transistors 102-105) handles rapid read/write operations, while the resistance switching element (202) maintains data persistence, allowing the system to achieve both fast access and data retention capabilities simultaneously.
Solution Approach 2:
The patent merges volatile and non-volatile memory technologies into a single integrated memory cell structure. The SRAM latch and resistance switching element are combined such that the latch provides fast access pathways while the resistance element preserves data state, creating a hybrid memory cell that exhibits both rapid access characteristics and non-volatile data retention.
2Reliability
If non-volatile memory (Flash) is used for data retention, then data is maintained without power, but access speed deteriorates
Solution Approach 1:
The memory system is divided into a non-volatile resistance switching element for data storage and a volatile latch circuit for rapid data access. The resistance element (202) maintains data persistence, while the latch circuit (transistors 102-105) enables fast read/write operations by providing direct access pathways, thereby resolving the speed limitation of traditional non-volatile memory.
Solution Approach 2:
The volatile latch circuit acts as an intermediary between the non-volatile resistance switching element and the external access lines. This intermediary structure allows data to be quickly transferred from the non-volatile element to the latch for rapid access, and back to the resistance element for retention, effectively bridging the speed gap of pure non-volatile memory.
3Reliability
If Flash memory is used for non-volatile storage, then data retention is improved, but power consumption increases
Solution Approach 1:
The memory system uses periodic or on-demand refreshing of the latch circuit rather than continuous power consumption. The volatile latch maintains data during active operations, and the non-volatile resistance element preserves data during standby or power-off periods, creating an energy-efficient operation mode where power is consumed only when data access is required.
Solution Approach 2:
The resistance switching element provides self-service data retention without requiring continuous power or refresh operations. Once data is written to the resistance element, it maintains its state autonomously without external intervention, eliminating the need for continuous power consumption associated with traditional volatile memory refresh cycles.
4Reliability
If resistance switching elements are added for non-volatile storage, then data retention is improved, but device complexity increases
Solution Approach 1:
The resistance switching element is merged with the existing SRAM latch circuit in a compact integrated structure. The shared transistor connections and common supply lines reduce the overall component count, allowing the hybrid volatile-non-volatile memory cell to achieve enhanced data retention without proportionally increasing circuit complexity.
Solution Approach 2:
The resistance switching element serves multiple functions: it acts as a non-volatile storage element, a programmable resistor for latch state control, and a data retention mechanism. This multi-functionality reduces the need for separate dedicated components, thereby limiting the increase in device complexity while achieving robust data retention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides fast access times and low energy consumption by maintaining non-volatile data even when power is removed, with the ability to quickly transfer data to volatile storage, enhancing storage capacity and reducing power consumption during standby states.
Implementation Method 1
a first resistance switching element coupled in series with said first transistor and programmable to have one of first and second resistive states
Data Source
Figure 1~2
Figure 3~5
Figure 6A~6B
AI summary
The invention concerns a memory device comprising at least one memory cell comprising: a first transistor (102) coupled between a first storage node (106) and a first supply line (GND, VDD); a second transistor (104) coupled between a second storage node and said first supply line (GND, VDD), control terminals of said first and second transistors being coupled to said second and first storage nodes respectively; a third transistor (110) coupled between said first storage node and a first access line (BLB) and controllable via a first control line (WL1); a fourth transistor (112, 712) coupled between said second storage node (108) and a second access line (BLB) and controllable via a second control line; and a first resistance switching element (202) coupled in series with said first transistor and programmable to have one of first and second resistive states.