Programmable Memory Anti-Fuse Unit With Efuse Correction
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Solution Overview
Problem
Conventional one-time programmable anti-fuse memory structures limit flexibility and redundancy due to their inability to correct programming errors, leading to complex circuit designs and increased layout area, which compromises reliability.
Innovation Solution
Incorporating an efuse between the anti-fuse programming transistor and a control transistor allows for both normal programming by breaking down the gate-source insulation layer and correction programming by fusing the efuse, enabling the anti-fuse unit to be programmed twice, thus correcting error bits and simplifying circuit and layout designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional anti-fuse units are used for one-time programming, then programming simplicity is maintained, but programming error correction capability is lost and layout area increases
Solution Approach 1:
The patent merges the anti-fuse programming transistor M0 and efuse EF into a single integrated anti-fuse unit. The anti-fuse transistor's gate insulation layer breakdown provides initial programming, while the series-connected efuse provides subsequent correction programming through its resistance change, eliminating the need for separate redundant bit circuits and reducing layout area.
Solution Approach 2:
The anti-fuse unit achieves multi-functionality by combining two programming mechanisms: the anti-fuse transistor M0 enables initial programming through gate insulation breakdown, while the efuse EF enables correction programming through resistance change. This single unit performs both primary programming and error correction functions that traditionally required separate circuits.
2Reliability
If redundant bits are added to correct programming results, then error correction capability is improved, but circuit complexity increases
Solution Approach 1:
The patent merges the correction function into the same anti-fuse unit structure by adding the efuse EF in series with the anti-fuse transistor M0. This integration eliminates the need for separate redundant bit circuits and their associated control logic, significantly reducing circuit complexity while maintaining error correction capability.
Solution Approach 2:
The anti-fuse unit achieves multi-functionality by combining two programming mechanisms: the anti-fuse transistor M0 enables initial programming through gate insulation breakdown, while the efuse EF enables correction programming through resistance change. This single unit performs both primary programming and error correction functions that traditionally required separate circuits.
3Ease of manufacture
If one-time programmable structures are used, then manufacturing cost is reduced, but flexibility and reprogrammability are limited
Solution Approach 1:
The patent introduces dynamic reprogrammability to the traditionally static one-time programmable anti-fuse structure. The efuse EF, connected in series with the anti-fuse transistor M0, enables the circuit to change its programming state dynamically. After initial programming via anti-fuse breakdown, the efuse can be programmed subsequently to correct errors or reprogram the unit, transforming a static OTP structure into a dynamically reprogrammable system.
Solution Approach 2:
The patent utilizes parameter changes in the efuse EF to enable reprogrammability. The efuse's resistance parameter can be changed from its initial state to a fused high-resistance state through subsequent programming. This parameter change allows the anti-fuse unit to transition from its initial programming state to a corrected or reprogrammed state, providing flexibility while maintaining standard CMOS manufacturing compatibility.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a smaller layout area, higher reliability, and increased flexibility while maintaining the original features of reliable and safe data storage, enhancing the applicability of the anti-fuse unit.
Implementation Method 1
The anti-fuse breaks down an insulation layer between a polysilicon layer and an N+ diffusion layer of a programming transistor to change (decrease) the resistance value between the two layers
Implementation Method 2
the efuse realizes chip programming by fusing the fuse and changing the resistance at both ends of the fuse according to the characteristics of electron migration
Data Source
AI summary
The present application discloses a programmable memory, wherein an anti-fuse unit thereof is formed by adding an efuse between an anti-fuse programming transistor and a control transistor of a conventional anti-fuse unit such that the anti-fuse unit can be programmed twice, that is, normal programming can be implemented by breaking down a gate-source insulation layer of the anti-fuse programming transistor, and correction programming can be further implemented by fusing the efuse such that correction programming can be performed on a normal programming result, thereby changing a logical state of the normally programmed anti-fuse unit. For the programmable memory, a reprogramming method can be directly used to correct an error bit, thereby simplifying circuit and layout designs, resulting in a smaller layout area and higher reliability, increasing the applicability and flexibility, while retaining original features of reliable and safe data of the anti-fuse unit.