Programmable Memory Hierarchy for Workload-Aware Data Movement

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Solution Overview

Problem

Conventional cache systems are workload-agnostic and inefficient, leading to inefficiencies in data access and movement, particularly in scenarios involving increasing data volumes, and are not scalable for evolving workloads like artificial intelligence and machine learning.

Innovation Solution

A programmable data storage memory hierarchy that includes a data movement controller to enable programmable data movement between memory buffers, leveraging existing cache and coherence infrastructures for workload-aware optimizations, allowing control over data residency and movement through programmable data movement commands.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If conventional cache systems are used with hierarchical arrangement, then data access is simplified through automatic management, but data movement efficiency deteriorates due to workload-agnostic control

Engineering Contradiction:
Improveautomatic data managementVSAvoiddata access efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent introduces a data movement controller that dynamically adjusts data movement operations based on workload characteristics. The controller receives workload information and programmatically controls data movement between cache levels, transforming the static hierarchical cache system into a dynamic one that adapts to different workload patterns, thereby improving data access efficiency while maintaining ease of operation through automated control.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If conventional hierarchical cache control is used, then system complexity is reduced through standardized management, but adaptability to different workloads deteriorates

Engineering Contradiction:
Improvecache management complexityVSAvoidworkload adaptability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent segments the cache control functionality into two parts: the conventional hierarchical cache management remains intact for standardized operation, while a separate data movement controller is introduced to handle workload-specific optimizations. This segmentation allows the system to maintain low complexity through standardized cache management while gaining adaptability through the programmable data movement controller that can be configured for different workload types.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If data movement is limited to internal cache hierarchy, then system simplicity is maintained, but performance optimization deteriorates for specific workloads

Engineering Contradiction:
Improvedata movement controlVSAvoidprocessing speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent introduces a data movement controller as an intermediary component between the conventional cache hierarchy and the processor. This intermediary receives data movement commands from the processor, analyzes workload characteristics, and intelligently controls data movement between cache levels and external memory. The intermediary maintains system simplicity by abstracting complex data movement logic while improving performance through workload-aware optimization of data transfer operations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12417178B2Programmable data storage memory hierarchy
Publication Date: 2025.09.16 ADVANCED MICRO DEVICES INC
  • US12417178B2 patent drawing
  • US12417178B2 patent drawing
  • US12417178B2 patent drawing

AI summary

Programmable data storage memory hierarchy techniques are described. In one example, a data storage system includes a memory hierarchy and a data movement controller. The memory hierarchy includes a hierarchical arrangement of a plurality of memory buffers. The data movement controller is configured to receive a data movement command and control data movement between the plurality of memory buffers based on the data movement command.