Programmable Memory Interleaving for Page Thrashing Reduction
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Solution Overview
Problem
Conventional memory address interleaving policies in multiple-bank memories lead to inefficiencies due to fixed mapping, resulting in significant page thrashing when different program streams access memory, as they often require accessing different rows of the same bank, causing delays and reduced performance.
Innovation Solution
A programmable memory address interleaving method that dynamically maps linear addresses to chip, bank, row, and column identifiers using a programmable register or BIOS, allowing for runtime adjustment of bit location mappings and incorporating logic operations like XOR to introduce pseudo-randomness, thereby reducing page thrashing by optimizing memory access patterns for different program streams.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a fixed interleaving policy is used for memory address translation, then the memory access pattern is simple and predictable, but different program streams experience significant page thrashing and performance degradation
Solution Approach 1:
The patent implements dynamic interleaving by allowing the address translation policy to change based on the active program stream. The system switches between different interleaving policies (e.g., row-major, column-major, diagonal) depending on the memory access patterns detected or specified for each program stream, making the translation mechanism adaptive rather than fixed.
Solution Approach 2:
The patent changes the parameters of the address translation function by introducing programmable translation tables that can be configured differentially for each program stream. These tables map linear addresses to physical addresses using different interleaving policies, allowing parameter variation without changing the fundamental translation mechanism.
2Productivity
If the same interleaving policy is used for all program streams, then the memory controller structure remains simple, but memory access efficiency deteriorates due to frequent row switching delays
Solution Approach 1:
The patent segments the memory controller functionality by introducing separate translation tables for different program streams. Each program stream has its own interleaving policy configured in dedicated translation tables, allowing independent optimization for each stream's memory access patterns without affecting others.
Solution Approach 2:
The system incorporates feedback mechanisms that monitor memory access patterns and adjust the interleaving policy accordingly. By detecting row switching behavior and page thrashing, the system can adapt the translation policy to reduce delays and improve access efficiency for each program stream.
3Reliability
If programmable interleaving policies are implemented, then page thrashing is reduced and memory access efficiency improves, but the system complexity and configuration requirements increase
Solution Approach 1:
The patent implements a universal address translation mechanism that can handle multiple interleaving policies through a single programmable framework. The same translation hardware structure supports different policies (row-major, column-major, diagonal, etc.) by loading different translation tables, providing multi-functionality without proportionally increasing hardware complexity.
Data Source
AI summary
A method includes receiving a linear address for accessing a multiple-bank memory, determining a first bit location of the linear address based on a first register value, and providing a bank identifier based on a value at the first bit location of the linear address. Another method includes receiving, at a memory controller coupled to a multiple-bank memory, input indicating a mapping of values at identified bit locations of a linear address to corresponding values of a memory address output. The memory address output includes a bank identifier based on a value at one or more of at least three bit locations of the linear address and a value of the input is programmable.