Programmable Memory Macro for In-Memory Data Processing
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Solution Overview
Problem
Current data storage and processing architectures face limitations due to communication and memory-access bottlenecks, energy inefficiency, and high non-recurring engineering costs associated with in-memory processing technologies.
Innovation Solution
A memory macro comprising a memory array and programmable periphery circuitry that processes manifest loop instructions to control data access, allowing for flexible and complex memory addressing without external address calculation units, thereby reducing costs and energy consumption while maintaining high throughput and low latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If in-memory processing technology is used to achieve high throughput and low latency, then data processing performance is improved, but non-recurring engineering cost increases significantly
Solution Approach 1:
The memory macro is designed to perform both traditional memory storage functions and in-memory processing operations using the same memory array structure. The programmable periphery circuitry enables the memory macro to execute manifest loop instructions and perform data processing operations directly on stored data, eliminating the need for separate specialized processing hardware while achieving high throughput and low latency performance
2Loss of time
If in-memory processing technology is used to enable real-time data processing, then data transfer time is reduced, but energy consumption increases
Solution Approach 1:
The invention merges the memory array with programmable periphery circuitry to create an integrated memory macro that can perform processing operations directly on stored data. This integration eliminates the need for separate data transfer operations between memory and processing units, reducing both data transfer time and the energy associated with moving data between components
3Adaptability or versatility
If programmable periphery circuitry is added to enable flexible memory addressing, then adaptability is improved, but device complexity increases
Solution Approach 1:
The periphery circuitry is designed with programmable control logic that can be configured through manifest loop instructions to perform different addressing modes and data processing operations. This dynamic programmability allows the same hardware structure to adapt to various memory access patterns and processing requirements without requiring multiple specialized circuits for each function
Data Source
Figure 1A
Figure 1B
Figure 2~3
AI summary
The present disclosure relates to a memory macro comprising a memory array and a periphery circuitry configured to read data from and/or write data to the memory array, wherein the periphery circuitry comprises a programmable circuitry causing the memory macro to access data stored in the memory array in accordance with manifest loop instructions; the programmable circuitry comprising a control logic configured to control the operation of the periphery circuitry in accordance with a set of parameters derived from the manifest loop instructions. The present disclosure further relates to a method for controlling the operation of a memory macro and to a processing system comprising the memory macro.