Programmable Memory Write Matrix for Flexible Array Placement
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Solution Overview
Problem
Conventional FPGA and structured ASIC designs face inefficiencies due to inaccuracies in predicting memory array configurations needed in integrated circuits, leading to suboptimal signal performance, increased power dissipation, and higher costs due to unnecessary memory arrays and longer data signal routing.
Innovation Solution
A reconfigurable memory circuit block that can be strategically placed throughout the integrated circuit, repurposing resources like flip-flops to adapt to different user designs without requiring additional redundant resources, allowing for optimized signal performance, power usage, and die area utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional FPGA and structured ASIC designs use fixed memory array configurations, then manufacturing is simpler, but signal performance deteriorates and power dissipation increases due to suboptimal placement
Solution Approach 1:
The patent implements reconfigurable memory array circuits that can dynamically change their configuration and placement locations within the integrated circuit. This allows the memory arrays to be strategically positioned close to logic circuit blocks during operation, reducing signal routing distances and power dissipation while maintaining manufacturing simplicity through a unified reconfigurable architecture
2Device complexity
If conventional designs place memory arrays at fixed locations, then device complexity is reduced, but signal performance worsens due to longer data signal routing
Solution Approach 1:
The reconfigurable memory array circuits can be dynamically placed at different locations within the integrated circuit based on design requirements. This dynamic placement capability allows memory arrays to be positioned optimally close to logic circuit blocks, significantly reducing data signal routing distances and improving signal performance without substantially increasing device complexity
Solution Approach 2:
The patent creates a universal reconfigurable memory array circuit that can serve multiple functions and be placed in multiple locations within the integrated circuit. This single multi-functional circuit block replaces the need for multiple fixed memory arrays, maintaining device complexity while enabling optimal signal performance through flexible placement
3Adaptability or versatility
If conventional designs use multiple fixed memory array configurations, then adaptability to different user designs is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements a universal reconfigurable memory array circuit that can be configured to serve different user designs and placed at various locations within the integrated circuit. This single multi-functional circuit block provides the adaptability of multiple specialized memory arrays while reducing device complexity and cost by eliminating redundant fixed configurations
Solution Approach 2:
The reconfigurable memory array circuits can dynamically adapt their configuration and placement location based on specific user design requirements. This dynamic adaptability allows a smaller number of versatile memory array circuits to replace multiple fixed configurations, reducing device complexity while maintaining high adaptability to different designs
4Ease of manufacture
If conventional designs place memory arrays far from logic circuit blocks, then manufacturing is easier, but interconnect resources increase and performance varies
Solution Approach 1:
The reconfigurable memory array circuits can be dynamically placed close to logic circuit blocks within the integrated circuit, minimizing interconnect resources and signal routing requirements. This dynamic placement capability reduces the quantity of interconnect materials needed while maintaining manufacturing ease through a standardized reconfigurable architecture
Data Source
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AI summary
An integrated circuit (100) includes a memory array circuit (101-104), flip-flop circuits (131-133, 140-155), and a write programmable matrix circuit (123). A first one of the flip-flop circuits (147) is coupled to store one of a first write address signal (WA1) or a first data input signal (DIN7). A second one of the flip-flop circuits (148) is coupled to store one of a second write address signal (WA0) or a second data input signal (DIN8). A write programmable matrix circuit (123) is coupled to receive signals stored in the flip-flop circuits. The write programmable matrix circuit is coupled to provide a subset of the signals stored in the flip-flop circuits to inputs of the memory array circuit (101-104) through option conductors in the write programmable matrix circuit during write operations to the memory array circuit.