Programmable Multi-Die Module Using One Die Type and TSV Links
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Solution Overview
Problem
Conventional multi-chip package implementations require multiple unique die designs, leading to increased costs and time due to the need for multiple tape-ins and mask sets, as well as complexities in troubleshooting and testing.
Innovation Solution
The use of a single die type with innovative configurations, such as through-silicon via (TSV) capabilities and interposers, allows for the creation of multi-die modules, reducing the number of required die types and simplifying test program development, thereby minimizing mask costs and improving design turnaround time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple unique die designs are used for multi-chip package implementation, then die-to-die connectivity and system functionality are achieved, but manufacturing cost and complexity increase due to multiple tape-ins and mask sets
Solution Approach 1:
The patent applies universality by designing a single die type that can serve multiple functions and positions within a multi-chip package. The programmable die is configured with multiple shoreline regions that can each be programmed to perform different connectivity functions (e.g., master shoreline, slave shoreline, general-purpose I/O), allowing one die design to replace multiple specialized die types while maintaining full system functionality and die-to-die connectivity
2Adaptability or versatility
If multiple unique die designs are used, then specific functional requirements are met, but manufacturing time and cost increase due to multiple tape-in processes
Solution Approach 1:
The patent applies dynamics through programmable configuration that allows the die to be dynamically reconfigured for different functions after manufacturing. The shoreline regions can be programmed via JTAG or other interfaces to change their behavior (master, slave, I/O modes) without physical reconfiguration, enabling rapid design iterations and reducing turnaround time while maintaining functional versatility
Solution Approach 2:
The patent applies preliminary action by pre-configuring the die with multiple shoreline regions during manufacturing that are capable of performing various functions. This preliminary structural preparation allows rapid post-manufacturing programming to achieve specific configurations without requiring multiple specialized die designs, thus reducing design turnaround time
3Adaptability or versatility
If multiple die types are used, then system functionality is achieved, but troubleshooting and testing become more complex
Solution Approach 1:
The patent applies homogeneity by using identical die types throughout the multi-chip package, all with the same shoreline region structures and programming interfaces. This uniformity simplifies troubleshooting and testing because all dies behave the same way and can be programmed identically, eliminating the need to develop and maintain separate test programs for different die types while still achieving full system functionality through configurational diversity
4Adaptability or versatility
If multiple die types are manufactured, then diverse functionality is achieved, but yield and cost efficiency decrease
Solution Approach 1:
The patent applies universality by manufacturing a single die type that can be programmed to perform multiple functions. This approach increases manufacturing yield because all dies are identical and can be produced in large volumes on the same wafer, and it maintains functional diversity through post-manufacturing programming of different shoreline regions rather than through physical die differentiation
Data Source
AI summary
Die configuration types are provided that may be used together with other instances of the design to create multi die modules.