Programmable Multiplexer Circuit for Constant Logic Output
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Solution Overview
Problem
Existing multiplexers in programmable logic devices (PLDs) face issues when driving unused logic pins to a logic high signal, as current methods either reduce connectivity or complicate silicon verification, particularly with half-latch approaches that are difficult to test and may not guarantee a logic high state during partial reconfiguration.
Innovation Solution
A selection circuit is designed with a first bank of transistors receiving input signals and coupled to memory cells, and a second bank of transistors with gates connected to another set of memory cells, allowing the circuit to be programmable for either a constant logic level or to select one of multiple input signals, eliminating the need for a dedicated connection to the power supply and improving connectivity and verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If one input pin is tied to power supply voltage to provide logic high signal, then logic high signal can be provided to unused logic pins, but connectivity of the interconnect multiplexer is reduced
Solution Approach 1:
The patent makes the power supply connection universal by allowing it to serve dual purposes: providing logic high signals to unused logic pins and serving as a regular routed signal when needed. The multiplexer can be programmed to either tie an input to VDD or route a signal through it, making the connection adaptable to different operational modes rather than being dedicated to a single function.
Solution Approach 2:
The patent introduces dynamic programmability to the multiplexer configuration, allowing the connection topology to change based on operational requirements. The device can be reconfigured via configuration bits to dynamically switch between providing a constant logic high and routing signals, enabling the system to adapt its connectivity structure rather than being fixed.
2Stability of the object's composition
If a half-latch approach is used to hold internal node at logic high, then logic high signal can be maintained, but silicon verification becomes difficult and state cannot be guaranteed during partial reconfiguration
Solution Approach 1:
The patent extracts the complexity of the half-latch mechanism and replaces it with a simpler, more verifiable approach. Instead of using a half-latch that requires complex verification, the invention uses a direct programmable connection to VDD with optional buffering, which is inherently more stable and easier to verify through standard testing methods while maintaining the logic high state reliably.
3Reliability
If interconnect multiplexer is programmed to always output logic high signal, then unused logic pins can be driven, but available connectivity is reduced regardless of routing needs
Solution Approach 1:
The patent creates a universal multiplexer structure where each multiplexer can function in multiple modes: routing signals between inputs and outputs, or providing a constant logic high to unused logic pins. This multi-functionality allows the same hardware resource to serve different purposes based on the design requirements, maximizing both pin driving capability and routing flexibility.
Solution Approach 2:
The patent enables dynamic reconfiguration of the multiplexer through programmable control, allowing the system to adapt its behavior based on whether logic pins are used or unused. The configuration can be changed via bitstream programming to switch between routing mode and constant logic high output mode, providing flexibility that static designs cannot achieve.
Data Source
AI summary
A selection circuit, such as a multiplexer circuit, programmable to hold the output signal at a constant logic level or select 1 of n input signals as the output signal is disclosed. A first bank of transistors receives the n input signals and is controlled by a first set of memory cells. A second bank of transistors is controlled by a second set of memory cells. At least two transistors of the second bank have gates are coupled to a complemented output of one of the second set of memory cells. Each transistor in the second bank is coupled to a subset of transistors of the first bank. An output stage is coupled to the second bank of transistors. A pair of serially coupled transistors has gates coupled to two memory cells of the second set that control the at least two transistors of the second bank. The output stage outputs the constant logic level signal when the serially coupled transistors are conducting, and outputs the selected input signal when the serially coupled transistors are not conducting.