Programmable Multiplexer Layout for Reduced Silicon Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As the need for multiplexers with a greater number of data input signals increases, the silicon real estate required grows exponentially, necessitating a solution to reduce the silicon space needed for multiplexer functionality, particularly for those with 4 or more data input signals.
Innovation Solution
The implementation of a programmable logic device using a multiplexer with half the number of data input ports and switch logic to emulate the functionality of a conventional multiplexer, where data input signals are configured to be either logical low, logical high, or a variable signal and its complement, allowing for efficient routing and reduced silicon usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of data input ports in a multiplexer is increased, then the multiplexing capability is improved, but the silicon real estate required increases exponentially
Solution Approach 1:
The patent divides a large multiplexer into multiple smaller multiplexers with fewer input ports. Each small multiplexer handles a subset of the total data inputs, and their outputs are combined through additional logic. This segmentation reduces the silicon area required for each individual multiplexer unit while achieving the same overall multiplexing capability.
Solution Approach 2:
The patent implements a hierarchical structure where smaller multiplexers are nested within a larger multiplexer architecture. The small multiplexers process groups of input signals, and their outputs feed into higher-level multiplexing stages. This nested arrangement allows efficient utilization of silicon real estate by organizing multiplexing functions at multiple levels.
2Area of stationary object
If the number of data input ports is reduced to decrease silicon usage, then the silicon real estate is reduced, but the multiplexing capability is degraded
Solution Approach 1:
The patent combines multiple small multiplexers with additional control logic to achieve the functionality of a large multiplexer. By merging the outputs of several small multiplexers and using selective gating, the system maintains full multiplexing capability despite each individual unit having fewer input ports.
Solution Approach 2:
The small multiplexer units are designed to be universal building blocks that can handle different input combinations through programmable control. Each small multiplexer can be configured to process different sets of inputs based on control signals, allowing the same hardware structure to provide versatile multiplexing functionality across multiple stages.
Data Source
AI summary
An implementation of multiplexer functionality using a multiplexer having half the number of input ports as it has possible output values is provided. A multiplexer having two data input ports performs the function of a multiplexer having four predetermined data input signals (A1, A2, A3, A4). In general, a multiplexer having only m data input ports performs the function of a multiplexer having twice as many predetermined data input signals A1, A2, . . . , Aj, where j=m*2. The multiplexer functionality may be implemented using a programmable device having one or more macrocells, an inverter and switches such as antifuses.