Programmable Multiplexer Select Delay for DDR Driver Duty Cycle
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Solution Overview
Problem
Existing double data rate (DDR) driver designs face limitations due to fixed delay elements, leading to potential data corruption and non-uniform duty cycles, which result in suboptimal performance and increased delays, especially in systems with varying cycle times and unbalanced duty cycle clocks.
Innovation Solution
A programmable two-to-one multiplexer select signal delay system is introduced, allowing for adjustable delays based on actual setup times and separate 50% duty-cycle clocks to ensure uniform data transfer, minimizing delays and optimizing DDR bus drivers for changing high-frequency requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed delay elements are used to meet multiplexer setup and hold time requirements, then data corruption is prevented under specific conditions, but the system cannot adapt to varying cycle times and experiences performance degradation
Solution Approach 1:
The patent applies dynamics by replacing fixed delay elements with programmable delay elements that can dynamically adjust their delay values based on the actual cycle time and operating conditions. This allows the system to adapt to varying cycle times while maintaining proper setup and hold time margins, preventing data corruption without performance degradation.
Solution Approach 2:
The patent changes the delay parameter from a fixed value to a programmable value that can be adjusted based on operating conditions. By making the delay element programmable, the system can optimize the delay value for different cycle times and bus skew conditions, maintaining reliability while improving adaptability.
2Reliability
If fixed delay elements are used to delay select signals for worst-case scenarios, then setup time requirements are met, but excessive delays are introduced reducing data transfer efficiency
Solution Approach 1:
The patent uses programmable delay elements that can dynamically adjust the select signal delay based on actual operating conditions rather than always using the worst-case delay value. This allows the system to meet setup time requirements when needed while minimizing delays under normal conditions, thereby improving data transfer efficiency.
Solution Approach 2:
The patent avoids excessive delay by using programmable delay elements that apply only the necessary delay amount rather than always applying the maximum delay required for worst-case scenarios. This partial action approach maintains reliability while improving productivity.
3Speed
If unbalanced duty cycle clocks are used to drive master-slave latches, then higher frequency operation is enabled, but non-uniform duty cycles in the data signal are introduced
Solution Approach 1:
The patent extracts the duty cycle non-uniformity problem by using separate 50% duty cycle clocks to drive the master and slave latches independently. By taking out the problematic unbalanced duty cycle clock and replacing it with two balanced clocks, the system can operate at higher frequencies while maintaining uniform duty cycles in the data signal.
Solution Approach 2:
The patent uses asymmetric clocking by providing separate clocks for master and slave latches with different phase relationships. This asymmetric approach allows each latch to be optimally clocked for high-speed operation while maintaining overall duty cycle uniformity in the data path.
Data Source
AI summary
A double data rate launch system and method in which the two-to-one multiplexer select signal delay is programmable and can be adjusted individually for each system. This allows the amount of delay to be minimized based on the actual set up time required, not the worst-case set-up time. The select signal to the multiplexer is delayed sufficiently to compensate for non-uniformity of duty cycle of data at the inputs to the multiplexer. Compensation of the non-uniformity allows the data on the wire to have a uniform duty cycle for all data transferred regardless of which latch is sourcing the data. The multiplexer that selects data from the two latches which are launching data on the edge of different clocks has a select line that is delayed by a variable amount to tune the select such that the data is clean at the input to the multiplexer on all ports.