Programmable Network Interface Device Multi-Protocol Support

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Solution Overview

Problem

Current network interface devices face inefficiencies in managing data transfers and protocol processing between host computing devices and networks, particularly in supporting multiple device interfaces and bus protocols, which can lead to increased resource consumption and latency.

Innovation Solution

A programmable interface for network interface devices is introduced, capable of supporting multiple device interfaces and bus protocols, including PCIe, CCIX, and NVMe, with features like DMA descriptor caching, address translation services, and adaptable scheduling to optimize data transfers and reduce resource usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a network interface device supports multiple device interfaces and bus protocols, then adaptability is improved, but device complexity increases

Engineering Contradiction:
Improvesupport for multiple device interfaces and bus protocolsVSAvoidresource consumption
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal interface layer that can operate with multiple bus protocols (PCIe, CCIX, NVLink, CXL) and device interfaces through a single programmable architecture. This layer provides protocol-agnostic data transfer capabilities, allowing the same hardware resource to serve multiple protocol requirements without requiring separate dedicated hardware for each protocol, thereby reducing overall device complexity while maintaining multi-protocol support

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If DMA descriptor caching is implemented, then data transfer efficiency is improved, but memory resource usage increases

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidmemory resource usage
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The patent implements descriptor caching with a hierarchical structure where frequently accessed DMA descriptors are cached in high-speed memory locally within the network interface device, while less frequently accessed descriptors remain in host memory. The system intelligently identifies and caches only the critical descriptors needed for active data transfers, providing local high-speed access where needed while minimizing overall memory consumption by not caching all descriptors simultaneously

Inventive Principle:
Principle #3Local quality

3Measurement precision

If address translation services are provided, then data transfer accuracy is improved, but processing overhead increases

Engineering Contradiction:
Improveaddress translation accuracyVSAvoidprocessing overhead
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent implements address translation services that pre-translate and cache address mappings before data transfers occur. The system establishes address translation tables and validates mappings in advance, so that during actual data transfers, the translated addresses are already ready and verified. This preliminary address preparation reduces the processing overhead during active transfers while maintaining translation accuracy, as the heavy translation work is performed beforehand rather than in real-time during data movement

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP4004753B1Programmable network interface device comprising a host computing device and a network interface device
Publication Date: 2023.12.13 XILINX INC
  • EP4004753B1 patent drawingFigure 1
  • EP4004753B1 patent drawingFigure 2
  • EP4004753B1 patent drawingFigure 3

AI summary

A network interface device (102) comprises a programmable interface (119) configured to provide a device interface with at least one bus between the network interface device (102) and a host device (101). The programmable interface (119) is programmable to support a plurality of different types of a device interface.