Programmable Networking Device Integrating FPGA Packet Processing
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Solution Overview
Problem
Existing communication networks face capacity limitations and suboptimal throughput due to the combination of hardware components dedicated primarily to packet processing with little processing power for management functions, leading to excessive communication between switching hardware and external servers, particularly in 4G and 5G networks.
Innovation Solution
Deploying programmable networking devices with embedded hardware such as FPGAs and GPUs that integrate multiple network functions, including packet processing and management, to securely route data packets and manage sessions using IPsec, minimizing excessive communication and enhancing control and user plane separation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware components are dedicated primarily to packet processing with little processing power for management functions, then packet processing capacity is improved, but communication overhead between switching hardware and external servers increases excessively
Solution Approach 1:
The patent combines packet processing functions and management functions into a single integrated hardware component. The management unit is implemented within the same device as the packet processing unit, eliminating the need for separate external servers and reducing communication overhead between different components.
Solution Approach 2:
The hardware component is designed to perform multiple functions simultaneously - both packet processing and management operations are handled by the same integrated unit. This multi-functional design allows the system to maintain high packet processing capacity while reducing the need for separate dedicated management hardware.
2Ease of operation
If user plane functions combine hardware components for packet processing with external servers for management functions, then functional separation is achieved, but throughput is limited due to capacity constraints
Solution Approach 1:
The patent merges the management unit and packet processing unit into a single integrated hardware component, allowing both control plane and user plane functions to be handled within the same device. This integration enables high throughput by eliminating the capacity constraints associated with separate external servers while maintaining functional separation through logical architecture.
3Reliability
If data traverses multiple network nodes for routing, then proper data routing is achieved, but processing efficiency decreases due to extra communication between switching hardware and external hosts
Solution Approach 1:
The patent integrates the management unit within the same hardware component as the packet processing unit, enabling data routing decisions to be made locally without requiring communication with external hosts. This integration maintains reliable data routing while significantly improving processing efficiency by eliminating unnecessary communication overhead.
Solution Approach 2:
The integrated hardware component performs self-service by handling both packet processing and management functions internally. The management unit can make routing decisions autonomously based on data packets received, without requiring external host intervention, thereby improving processing efficiency while maintaining routing accuracy.
Data Source
AI summary
Programmable networking devices configured to perform various packet processing functions for packet filtration, control and user plane separation (CUPS), user plane function (UPF), pipeline processing, etc. IPsec is utilized to secure control and data packets traversing the programmable networking device. Field-programmable gate arrays (FPGAs) are configured with one or more host servers and software-based network interfaces (softMAC).