Programmable NIC Virtual Switch with Hardware Header Parsing
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Solution Overview
Problem
Existing hardware acceleration solutions for virtual switches in cloud networks lack flexibility to adapt to rapid application requirements and iterations, leading to suboptimal performance and inability to meet evolving network demands.
Innovation Solution
Deploy a virtual switch in software form on a programmable network card device, equipped with a message parsing acceleration module and hardware message queue based on programmable hardware, to parse message headers and reduce parsing costs, allowing flexible application requirements and rapid iteration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware logic is implemented with ASIC, then forwarding performance is improved through hardware acceleration, but adaptability deteriorates as the logic cannot be modified
Solution Approach 1:
The patent implements a hybrid architecture where the virtual switch control logic runs as software on a programmable processor rather than fixed hardware. This allows the forwarding logic to be dynamically updated and reconfigured through software, combining hardware acceleration for message parsing with software flexibility for adaptability.
Solution Approach 2:
The patent introduces a programmable processor as an intermediary between the hardware message queue and the virtual switch logic. This mediator enables flexible software-based control while maintaining hardware acceleration capabilities, resolving the contradiction between fixed hardware performance and software adaptability.
2Adaptability or versatility
If hardware logic is implemented with FPGA, then adaptability is improved through reconfigurability, but device complexity increases due to development cycle and hardware resource constraints
Solution Approach 1:
The patent replaces complex FPGA-based hardware logic with a simpler programmable processor running virtual switch software. This substitution reduces device complexity and development overhead while maintaining flexibility through software programming, avoiding the resource constraints and complexity of FPGA implementations.
3Adaptability or versatility
If virtual switch is implemented in software on general-purpose CPU, then adaptability is improved, but forwarding performance deteriorates due to lack of hardware acceleration
Solution Approach 1:
The patent segments the virtual switch functionality into two parts: hardware message queue for high-speed message reception and buffering, and software-based virtual switch control logic on a programmable processor for flexible forwarding decisions. This segmentation enables both hardware acceleration and software adaptability to coexist.
Solution Approach 2:
The hardware message queue performs preliminary actions by pre-processing and buffering incoming messages before they reach the virtual switch control logic. This preliminary hardware processing reduces the burden on the software processor while maintaining flexibility in the forwarding decisions.
Data Source
AI summary
Embodiments of the present disclosure provide a message processing method, a programmable network card device, a physical server, and a storage medium. In the embodiments of the present disclosure, a virtual switch in software form is deployed on the programmable network card device, and a message parsing acceleration module and a hardware message queue providing message parsing service for the virtual switch are implemented on the programmable network card device based on programmable hardware. The embodiments of the present disclosure can greatly reduce the message parsing cost of the virtual switch and achieve high message forwarding performance. At the same time, all operations except parsing of the header information of the message are performed by the virtual switch in software form, which can meet flexible application requirements and ensure rapid iteration and evolution of the application requirements.