Programmable Network on Chip Routing via SAT Solver

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Solution Overview

Problem

Conventional network on chip (NOC) designs require a fixed and customized topology, which limits adaptability to different circuit designs and does not effectively manage Quality of Service (QOS) parameters, potentially leading to deadlock conditions.

Innovation Solution

A programmable NOC within an integrated circuit (IC) that determines routing solutions using Quality of Service parameters and satisfiability (SAT) solvers to generate expressions representing data flows, routing constraints, and QOS parameters, ensuring deadlock-free routes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a fixed and customized NOC topology is used, then the NOC can be optimized for specific application requirements, but it lacks adaptability to different circuit designs

Engineering Contradiction:
ImproveNOC performance optimizationVSAvoidadaptability to different circuit designs
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements a programmable NOC architecture where routing paths can be dynamically configured and reconfigured based on different circuit designs and QOS requirements. The system transitions from static fixed topology to dynamic programmable topology, allowing the NOC to adapt to various master-slave configurations while maintaining optimized performance for each specific application.

Inventive Principle:
Principle #15Dynamics

2Device complexity

If conventional fixed topology NOC is used, then implementation is simpler, but it cannot effectively manage QOS parameters and may lead to deadlock conditions

Engineering Contradiction:
ImproveNOC implementation complexityVSAvoiddeadlock-free operation and QOS management
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces a SAT solver as an intermediary component that acts as a routing controller. This solver takes QOS parameters and routing constraints as input, processes them through logical expressions, and generates deadlock-free routing solutions. The SAT solver mediates between the complex QOS management requirements and the NOC routing implementation, ensuring reliable operation without requiring complex manual configuration.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Manufacturing precision

If custom built NOC is used for ASIC, then the NOC can be precisely tailored to application requirements, but it increases manufacturing complexity and time

Engineering Contradiction:
ImproveNOC customization precisionVSAvoidmanufacturing complexity and time
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent creates a universal programmable NOC platform that can serve multiple different circuit designs and applications. Instead of manufacturing custom NOC for each ASIC application, the same programmable NOC hardware can be configured through software to meet different QOS requirements and routing needs, significantly reducing manufacturing complexity and time while maintaining precise tailoring capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS10628547B1Routing circuit designs for implementation using a programmable network on chip
Publication Date: 2020.04.21 XILINX INC
  • US10628547B1 patent drawing
  • US10628547B1 patent drawing
  • US10628547B1 patent drawing

AI summary

Routing a circuit design for implementation in an integrated circuit having a programmable network on chip can include determining Quality of Service (QOS) parameters for data flows of a circuit design, wherein the data flows involve transfers of data between masters and slaves through the programmable network on chip and generating, using a processor, an expression having a plurality of variables representing the data flows, routing constraints, and the QOS parameters. A routing solution can be determined using the processor for the data flows of the circuit design by initiating execution of a SAT solver using the expression.