Programmable ODT Timing in Multi-Rank Memory Buses
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Solution Overview
Problem
Current memory subsystems face challenges in controlling power consumption and signal quality due to the lack of on-die termination (ODT) in multi-rank memory systems, especially with increased memory densities, leading to signal degradation from reflections without ODT in standard packaging solutions, and existing ODT solutions are costly and limited in providing flexible termination settings for asymmetric topologies.
Innovation Solution
Implementing programmable ODT latency settings that allow memory devices to selectively engage ODT based on rank and transaction type, using programmable timing settings to adjust ODT turn-on and turn-off times, enabling flexible ODT control for both Read and Write operations, even in non-symmetric and unbalanced loading scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ODT is enabled in multi-rank memory systems, then signal quality is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic ODT control where the termination setting is changed based on the memory access pattern. The system transitions between different ODT states (enabled/disabled) depending on whether the access is intra-rank or inter-rank, allowing the system to adapt its power consumption and signal quality characteristics to the current operational context
Solution Approach 2:
The patent applies ODT selectively to specific ranks based on the access pattern. When an intra-rank access is detected, ODT is enabled only for that particular rank rather than all ranks, providing localized signal quality improvement while minimizing overall power consumption impact
2Use of energy by moving object
If ODT is disabled to reduce power consumption, then power consumption decreases, but signal degradation from reflections increases
Solution Approach 1:
The patent extracts the ODT function from being continuously enabled and instead applies it only when needed. By detecting intra-rank access patterns, the system extracts and applies the termination function selectively to prevent signal reflections only in the scenarios where they would occur, rather than maintaining continuous termination
3Adaptability or versatility
If additional ODT pins are added to provide flexible termination settings, then termination flexibility is improved, but device complexity increases
Solution Approach 1:
The patent makes the existing ODT pin multi-functional by enabling it to operate in different modes (enabled/disabled) based on the memory access pattern. The same physical pin serves multiple purposes: providing termination when needed for intra-rank accesses and being disabled for inter-rank accesses, eliminating the need for additional dedicated pins
Data Source
AI summary
On-die termination (ODT) control enables programmable ODT latency settings. A memory device can couple to an associated memory controller via one or more buses shared by multiple memory devices organized ranks of memory. The memory controller generates a memory access command for a target rank. In response to the command, memory devices can selectively engage ODT for the memory access operation based on being in the target rank or a non-target rank, and based on whether the access command includes a Read or a Write. The memory device can engage ODT in accordance with a programmable ODT latency setting. The programmable ODT latency setting can set different ODT timing values for Read and Write transactions.