Programmable Packet Scheduler Using Deficit Round Robin

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Solution Overview

Problem

Conventional packet scheduling methods often lead to unfair allocation of bandwidth resources in transmission ports, necessitating an improved approach for efficient and fair sharing of these resources.

Innovation Solution

A programmable weighted fair queuing scheduler employing deficit round robin (DRR) is used for packet scheduling, allowing for concurrent, mutually-independent scheduling across multiple destination ports with optional strict-priority and weighted DRR flows, ensuring fair bandwidth allocation through Weighted Fair Queuing (WFQ).

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional packet scheduling methods are used, then the scheduling process is simple, but the bandwidth allocation is unfair

Engineering Contradiction:
Improvefairness of bandwidth allocationVSAvoidscheduling mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the bandwidth allocation mechanism into multiple independent DRR flows, each with its own deficit counter and weight. This segmentation allows fair bandwidth allocation across multiple flows while keeping each flow's scheduling logic relatively simple and modular.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces weight parameters and deficit counters as configurable parameters to control bandwidth allocation. By changing these parameters, the system can achieve fair bandwidth distribution without fundamentally changing the scheduling mechanism's structure.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If Weighted Fair Queuing is implemented for fair bandwidth sharing, then bandwidth fairness is improved, but the scheduling complexity increases

Engineering Contradiction:
Improvebandwidth fairnessVSAvoidscheduling algorithm complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent replaces complex Weighted Fair Queuing calculations with a simpler Deficit Round Robin mechanism that uses integer arithmetic. Instead of calculating proportional bandwidth shares continuously, the system uses discrete deficit counters that are incremented by weight values and decremented by packet sizes, achieving similar fairness with simpler operations.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

Each DRR flow maintains its own deficit counter and serves itself based on its accumulated deficit. The scheduling algorithm simply selects the flow with the highest deficit counter, allowing each flow to self-regulate its bandwidth consumption without complex centralized control.

Inventive Principle:
Principle #25Self-service

3Productivity

If partial data packet transmission is enabled, then transmission efficiency is improved, but fairness characteristics may be compromised

Engineering Contradiction:
Improvetransmission efficiencyVSAvoidfairness characteristics
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent pushes back remaining packet portions to the tail of the same flow's queue before completing transmission. This preliminary action ensures that the flow will be served again in the next scheduling round, maintaining fairness while allowing partial packet transmission to improve efficiency.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system uses feedback from the deficit counter mechanism to track bandwidth consumption. When a flow transmits a partial packet, the deficit counter reflects the remaining bandwidth entitlement, ensuring that the flow receives fair treatment in subsequent scheduling decisions.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS8943236B1Packet scheduling using a programmable weighted fair queuing scheduler that employs deficit round robin
Publication Date: 2015.01.27 AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE LTD
  • US8943236B1 patent drawing
  • US8943236B1 patent drawing
  • US8943236B1 patent drawing

AI summary

The disclosed packet scheduler implements the deficit round robin (DRR) approximation of weighted fair queuing (WFQ), and is capable of achieving complete fairness across several hundred source flows, for example, each of which can be mapped to one of several destination ports. In addition to achieving fairness, the packet scheduler allows the user to map one or more optional strict-priority flows to each port. The packet scheduler keeps these strict-priority flows “outside” of the group of flows for which fairness is enforced. Each destination port can be optionally configured to chop its data packets into sub-packet pieces. The packet scheduler works in two mutually orthogonal dimensions: (1.) it selects destination ports based on a round-robin scheme, or using another method, such as guaranteed rate port scheduling (GRPS), and (2.) it implements optional strict-priority scheduling, and DRR scheduling.